Method for reduction of possible renderable graphics primitive shapes for rasterization
    61.
    发明授权
    Method for reduction of possible renderable graphics primitive shapes for rasterization 有权
    减少用于光栅化的可能的可渲染图形原始形状的方法

    公开(公告)号:US06975317B2

    公开(公告)日:2005-12-13

    申请号:US10096090

    申请日:2002-03-12

    IPC分类号: G06T15/50 G06T15/40

    CPC分类号: G06T15/80 G06T11/40

    摘要: A graphics system and method for rendering a plurality of triangles. Information regarding the triangle may first be received. The method may then determine the longest edge or major edge of the triangle and also determine the direction or axis of the longest edge of the triangle. The method may then perform edge walking on the major edge (e.g., along the axis of the major edge) of the triangle, followed by span walking. The edge walking is preferably always performed on the major or longest edge of the triangle, prior to the span walking, and regardless of the orientation of the major edge of the triangle. This operates to load balance the edge walker and the span walker for the plurality of triangles.

    摘要翻译: 一种用于渲染多个三角形的图形系统和方法。 可以首先接收关于三角形的信息。 该方法然后可以确定三角形的最长边缘或主边缘,并且还确定三角形的最长边缘的方向或轴线。 然后,该方法可以在三角形的主边缘(例如,沿着主边缘的轴线)执行边缘行走,随后进行跨度行走。 边缘行走优选总是在跨度行走之前在三角形的主要或最长边缘执行,并且不管三角形的主边缘的取向如何。 这用于对多个三角形负载平衡边缘步行者和跨度步行器。

    Graphics primitive size estimation and subdivision for use with a texture accumulation buffer
    62.
    发明授权
    Graphics primitive size estimation and subdivision for use with a texture accumulation buffer 有权
    用于纹理累积缓冲区的图形原始尺寸估计和细分

    公开(公告)号:US06914610B2

    公开(公告)日:2005-07-05

    申请号:US09861192

    申请日:2001-05-18

    IPC分类号: G06T15/04 G09G5/36 G09G5/00

    CPC分类号: G06T11/40 G06T15/04 G09G5/363

    摘要: A graphics system configured to apply multiple layers of texture information to primitives. The graphics system receives parameters defining a primitive and performs a size test on the primitive. If the size test cannot guarantee that a fragment size of the primitive is less than or equal to a fragment capacity of a texture accumulation buffer, the primitive is divided into subprimitives, and the graphics system applies the multiple layers of texture to fragments which intersect the primitive. The graphics system switches from a current layer to the layer next when it has applied textures corresponding to the current layer to all the fragments intersecting the primitive. The graphics system stores color values associated with the primitive fragments in the texture accumulation buffer between the application of successive texture layers.

    摘要翻译: 图形系统被配置为将多层纹理信息应用于原语。 图形系统接收定义原语的参数,并对原语进行大小测试。 如果大小测试不能保证原语的片段大小小于或等于纹理累加缓冲区的片段容量,则将原语划分为子标识符,并且图形系统将多层纹理应用于与 原始。 当图形系统将与当前层对应的纹理应用于与图元相交的所有片段时,图形系统将从当前图层切换到该图层。 图形系统在连续纹理层的应用之间存储与纹理累积缓冲器中的原始片段相关联的颜色值。

    Method for rasterizing graphics for optimal tiling performance
    63.
    发明授权
    Method for rasterizing graphics for optimal tiling performance 有权
    用于光栅化图形以获得最佳平铺性能的方法

    公开(公告)号:US06900803B2

    公开(公告)日:2005-05-31

    申请号:US10096346

    申请日:2002-03-12

    IPC分类号: G06T11/40 G06T17/20

    CPC分类号: G06T11/40

    摘要: A graphics system and method are disclosed that may optimize the rate of pixel generation to match the rate at which a memory may be designed to receive pixel data. If a memory is configured to store multiple pixels substantially simultaneously, it may be advantageous to render an equivalent number of pixels substantially simultaneously and at the same rate. An edge walker that utilizes multiple sets of accumulators to generate multiple scan lines substantially simultaneously and a span walker that utilizes multiple sets of accumulators to render multiple pixel values substantially simultaneously is described.

    摘要翻译: 公开了可以优化像素生成速率以匹配可设计存储器以接收像素数据的速率的图形系统和方法。 如果存储器被配置为基本上同时存储多个像素,则基本上同时且以相同的速率渲染等效数量的像素可能是有利的。 描述了利用多组累加器基本上同时产生多个扫描线的边缘步行器,以及利用多组累加器基本上同时呈现多个像素值的跨度步行器。

    End point value correction when traversing an edge using a quantized slope value
    64.
    发明授权
    End point value correction when traversing an edge using a quantized slope value 有权
    使用量化斜率值遍历边缘时的终点值校正

    公开(公告)号:US06867778B2

    公开(公告)日:2005-03-15

    申请号:US10085635

    申请日:2002-02-28

    IPC分类号: G06T11/20 G06T15/50

    CPC分类号: G06T11/40 G06T15/80

    摘要: A system and method for rendering a polygon, such as a triangle. The method may comprise receiving geometry data (or vertex data) defining vertices of the polygon. The method may compute initial vertex x,y values at end points proximate to each of the vertices of the polygon, and a slope value along each edge of the polygon. The computed slope may be a quantized slope value having a first number of bits of precision. The first number of bits of precision may produce inaccuracies for interpolated x,y values computed at the end points of an edge of the polygon. The method may then interpolate x,y values along each respective edge of the polygon using the computed slope along the respective edge of the polygon. Finally the method may store final x,y values for each respective edge of the polygon. The final x,y values comprise the interpolated x,y values for non-end points of the respective edge, and the computed initial vertex x,y values for each of the end points of the respective edge. The operation of storing the computed initial vertex x,y values for each of the end points of the respective edge, instead of using interpolated x,y values at the end points, operates to prevent inclusion of an extraneous pixel and/or exclusion of a pixel within the polygon.

    摘要翻译: 用于渲染多边形(如三角形)的系统和方法。 该方法可以包括接收定义多边形顶点的几何数据(或顶点数据)。 该方法可以在靠近多边形的每个顶点的端点处计算初始顶点x,y值,以及沿多边形的每个边缘的斜率值。 所计算的斜率可以是具有第一数位精度的量化斜率值。 对于在多边形边缘的端点处计算出的内插x,y值,第一个精度位可能会产生不准确。 然后,该方法可以使用沿多边形的相应边缘的计算斜率来内插多边形的每个相应边缘的x,y值。 最后,该方法可以存储多边形的每个相应边缘的最终x,y值。 最终的x,y值包括相应边缘的非端点的内插x,y值以及相应边缘的每个端点的计算的初始顶点x,y值。 存储相应边缘的每个端点的计算的初始顶点x,y值而不是在端点处使用内插的x,y值的操作,以防止包含外部像素和/或排除 多边形内的像素。

    Graphics data synchronization with multiple data paths in a graphics accelerator
    65.
    发明授权
    Graphics data synchronization with multiple data paths in a graphics accelerator 有权
    图形数据同步与图形加速器中的多个数据路径

    公开(公告)号:US06864892B2

    公开(公告)日:2005-03-08

    申请号:US10093835

    申请日:2002-03-08

    CPC分类号: G09G5/36 G06T15/005

    摘要: A system and method for preserving the order of data items through a divergence-and-reconvergence of two or more paths in a hardware device. A host processor may write a first token to a first path in the hardware device. A convergence unit in the hardware device may receive and store the first token in a synchronization register. The host processor may poll the synchronization register to determine when the first token arrives in the synchronization register. In response to determining that the first token has arrived in the synchronization register, the host processor may safely write a sequence of one or more data items to a second path in the hardware device.

    摘要翻译: 一种用于通过硬件设备中两个或多个路径的发散和再聚合来保持数据项的顺序的系统和方法。 主处理器可以将第一令牌写入硬件设备中的第一路径。 硬件设备中的会聚单元可以将第一令牌接收并存储在同步寄存器中。 主处理器可以轮询同步寄存器以确定第一个令牌何时到达同步寄存器。 响应于确定第一令牌已经到达同步寄存器,主处理器可以安全地将一个或多个数据项的序列写入硬件设备中的第二路径。

    System and method for performing scale and bias operations by preclamping input image data
    66.
    发明授权
    System and method for performing scale and bias operations by preclamping input image data 有权
    通过预压缩输入图像数据进行缩放和偏移操作的系统和方法

    公开(公告)号:US06847378B2

    公开(公告)日:2005-01-25

    申请号:US10093364

    申请日:2002-03-07

    IPC分类号: G06T3/40 G09G5/36 G09G5/02

    CPC分类号: G06T3/4007 G09G5/363

    摘要: In one embodiment, a scale and bias unit for use in a graphics system includes a preclamping unit configured to receive an input and to responsively generate an output value equal to a first value if the input is within a first input range. The scale and bias unit also includes a processing unit coupled to the preclamping unit and configured to perform a calculation on the input to generate the output value. The processing unit does not perform the calculation if the input is within the first input range.

    摘要翻译: 在一个实施例中,用于图形系统的比例尺和偏置单元包括预压缩单元,其被配置为接收输入并且如果输入在第一输入范围内则响应地产生等于第一值的输出值。 缩放和偏置单元还包括耦合到预压单元并被配置为对输入执行计算以产生输出值的处理单元。 如果输入在第一输入范围内,则处理单元不执行计算。

    Vertex assembly buffer and primitive launch buffer
    67.
    发明授权
    Vertex assembly buffer and primitive launch buffer 有权
    顶点汇编缓冲区和原始启动缓冲区

    公开(公告)号:US06816161B2

    公开(公告)日:2004-11-09

    申请号:US10060969

    申请日:2002-01-30

    IPC分类号: G06F1300

    CPC分类号: G06T15/005

    摘要: A graphics system and method for processing geometry compressed, three-dimensional graphics data are disclosed. After transforming and lighting each vertex, a vertex data stream is decompressed using connectivity information, and vertexes are reassembled into geometric primitives. The connectivity information may include mesh buffer references, vertex tags, or other types of information. Independent buffers, queues, and/or caches are used to simultaneously store: (a) vertex data for the next several primitives, (b) vertex data that will be reused, (c) vertex tags, (d) control tags, (e) vertex data being assembled into a primitive, and (f) an assembled primitive ready to be launched. The assembled primitive may be clip tested for visibility in a defined viewport, before investing time to have the primitive processed into pixel data for display. The independent buffers, queues, and/or caches may also enable the vertex processing steps to be performed in parallel and at different rates.

    摘要翻译: 公开了用于处理几何压缩的三维图形数据的图形系统和方法。 在对每个顶点进行变换和点亮之后,使用连通性信息解压缩顶点数据流,并将顶点重新组合成几何图元。 连接信息可以包括网格缓冲器引用,顶点标签或其他类型的信息。 独立缓冲区,队列和/或高速缓存用于同时存储:(a)下一个原语的顶点数据,(b)将被重用的顶点数据,(c)顶点标签,(d)控制标签,(e )顶点数据被组装成原始图形,(f)准备启动的组合原始图形。 在投入时间以将原始图像处理成像素数据进行显示之前,组合的原始图像可以在定义的视口中进行剪辑测试。 独立缓冲器,队列和/或高速缓存也可以使顶点处理步骤以并行且不同的速率执行。

    Performance texture mapping by combining requests for image data
    68.
    发明授权
    Performance texture mapping by combining requests for image data 有权
    通过组合图像数据请求来执行纹理映射

    公开(公告)号:US06812928B2

    公开(公告)日:2004-11-02

    申请号:US10060978

    申请日:2002-01-30

    IPC分类号: G09G539

    摘要: An optimizing unit for use with an interleaved memory and suitable for use in a computer graphics system is described. The unit utilizes knowledge of the repetitive and predictable nature of texture buffer accesses to potentially reduce the number of memory fetches. The unit maintains a queue of pending requests for tiles of data from the memory, and predicts the retrieval of redundant data within short sequences of requests. The redundant data is retrieved from the memory once, and repeated as necessary from local temporary storage registers.

    摘要翻译: 描述了一种用于交错存储器并适用于计算机图形系统的优化单元。 该单元利用纹理缓冲器访问的重复性和可预测性质的知识来潜在地减少存储器提取的数量。 该单元维护来自存储器的数据块的待处理请求队列,并且预测在短序列请求内检索冗余数据。 冗余数据从存储器中检索一次,并根据需要从本地临时存储寄存器重复。

    System and method for handling display device requests for display data from a frame buffer
    69.
    发明授权
    System and method for handling display device requests for display data from a frame buffer 有权
    用于处理从帧缓冲器显示数据的显示设备请求的系统和方法

    公开(公告)号:US06806883B2

    公开(公告)日:2004-10-19

    申请号:US10094930

    申请日:2002-03-11

    IPC分类号: G06F1318

    摘要: A graphics system may include a frame buffer, a processing device coupled to access data in the frame buffer, a frame buffer interface coupled to the frame buffer, and an output controller configured to assert a request for display data to provide to a display device. The frame buffer interface may receive the request for display data from the output controller and delay providing the request for display data to the frame buffer if the processing device is currently requesting access to a portion of the frame buffer targeted by the request for display data. For example, if the frame buffer includes several memory banks and the request for display data targets a first bank, the frame buffer interface may delay providing the request for display data to the frame buffer if the processing device is currently requesting access to the first bank.

    摘要翻译: 图形系统可以包括帧缓冲器,耦合到访问帧缓冲器中的数据的处理设备,耦合到帧缓冲器的帧缓冲器接口,以及输出控制器,被配置为断言显示数据的请求以提供给显示设备。 帧缓冲器接口可以从输出控制器接收对显示数据的请求,并且如果处理设备正在请求访问由显示数据请求所针对的帧缓冲区的一部分,则向帧缓冲器提供对显示数据的请求的延迟。 例如,如果帧缓冲器包括多个存储体并且显示数据的请求针对第一存储体,则如果处理设备正在请求访问第一存储体,则帧缓冲器接口可以延迟向帧缓冲器提供对显示数据的请求 。

    Synchronizing multiple display channels
    70.
    发明授权
    Synchronizing multiple display channels 有权
    同步多个显示通道

    公开(公告)号:US06784881B2

    公开(公告)日:2004-08-31

    申请号:US10037410

    申请日:2002-01-04

    IPC分类号: G09G500

    CPC分类号: G06F3/1431 G09G5/12 G09G5/363

    摘要: A graphics system that is configured to synchronize a slave display channel to a master display channel may include a master display timing generator configured to provide a frame event indication and a slave display timing generator. The slave display timing generator may be configured to receive the frame event indication and, in response to receiving the frame event indication during its active display period, the slave display timing generator may be configured to wait until its current active display period ends and then jump to its synchronization point. Alternatively, the slave display timing generator may be configured to jump to its synchronization point immediately or after the end of the current horizontal line, and any remaining display information in an interrupted frame may be displayed during the next active display period.

    摘要翻译: 被配置为将从属显示通道同步到主显示通道的图形系统可以包括被配置为提供帧事件指示和从属显示定时发生器的主显示定时发生器。 从显示定时发生器可以被配置为接收帧事件指示,并且响应于在其有效显示周期期间接收帧事件指示,从属显示定时发生器可以被配置为等待直到其当前活动显示周期结束然后跳转 到其同步点。 或者,从显示定时发生器可以被配置为立即或在当前水平行的结束之后跳转到其同步点,并且可以在下一活动显示周期期间显示中断帧中的任何剩余显示信息。