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1.发明授权Graphics primitive size estimation and subdivision for use with a texture accumulation buffer 有权用于纹理累积缓冲区的图形原始尺寸估计和细分公开(公告)号：US06914610B2
公开(公告)日：2005-07-05
申请号：US09861192
申请日：2001-05-18
申请人： Michael G. Lavelle , Wayne A. Morse , Rangit S. Oberoi , David C. Kehlet , Michael A. Wasserman , Brian D. Emberling , Roger C. Swanson
发明人： Michael G. Lavelle , Wayne A. Morse , Rangit S. Oberoi , David C. Kehlet , Michael A. Wasserman , Brian D. Emberling , Roger C. Swanson
摘要： A graphics system configured to apply multiple layers of texture information to primitives. The graphics system receives parameters defining a primitive and performs a size test on the primitive. If the size test cannot guarantee that a fragment size of the primitive is less than or equal to a fragment capacity of a texture accumulation buffer, the primitive is divided into subprimitives, and the graphics system applies the multiple layers of texture to fragments which intersect the primitive. The graphics system switches from a current layer to the layer next when it has applied textures corresponding to the current layer to all the fragments intersecting the primitive. The graphics system stores color values associated with the primitive fragments in the texture accumulation buffer between the application of successive texture layers.
摘要翻译： 图形系统被配置为将多层纹理信息应用于原语。 图形系统接收定义原语的参数，并对原语进行大小测试。 如果大小测试不能保证原语的片段大小小于或等于纹理累加缓冲区的片段容量，则将原语划分为子标识符，并且图形系统将多层纹理应用于与 原始。 当图形系统将与当前层对应的纹理应用于与图元相交的所有片段时，图形系统将从当前图层切换到该图层。 图形系统在连续纹理层的应用之间存储与纹理累积缓冲器中的原始片段相关联的颜色值。
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2.发明授权Multi-texturing by walking an appropriately-sized supertile over a primitive 有权通过在原始图像上行走适当尺寸的超重物进行多纹理化公开(公告)号：US07023444B2
公开(公告)日：2006-04-04
申请号：US10393528
申请日：2003-03-20
申请人： Brian D. Emberling , Michael G. Lavelle , Assana M. Fard , Nandini Ramani , David C. Kehlet , Michael A. Wasserman , Ewa M. Kubalska , Mark E Pascual
发明人： Brian D. Emberling , Michael G. Lavelle , Assana M. Fard , Nandini Ramani , David C. Kehlet , Michael A. Wasserman , Ewa M. Kubalska , Mark E Pascual
IPC分类号： G06T11/40
CPC分类号： G06T15/04
摘要： A rendering unit positions a supertile so that it intersects a primitive. The rendering unit repeatedly walks over bins of the supertile, applying a layer of texture to the bins of the supertile in each iteration of said repeated walking. The rendering unit advances to the next texture layer after having applied the current texture layer to each candidate bin of the supertile. The results of each texture layer application to the bins may be stored in a texture accumulation buffer. The size of the supertile corresponds to the size of the texture accumulation buffer. After applying a last layer of texture to the bins of the supertile, the supertile may be advanced to a new position. The rendering unit traverses the primitive with the supertile so that the union of areas visited by the supertile covers the primitive.
摘要翻译： 渲染单元定位一个supertile，以便它与一个原语相交。 渲染单元重复地移动超重物料箱，在所述重复步行的每次迭代中将一层纹理施加到上层的仓上。 渲染单元在将当前纹理层应用于上层的每个候选块之后前进到下一个纹理层。 每个纹理层应用于存储区的结果可以存储在纹理累积缓冲器中。 supertile的大小对应于纹理累积缓冲区的大小。 将最后一层纹理应用于上层的仓后，超级可以提前到一个新的位置。 渲染单元用优先级遍历原始图像，使得由supertile访问的区域的联合覆盖原始图像。
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3.发明授权Graphics data synchronization with multiple data paths in a graphics accelerator 有权图形数据同步与图形加速器中的多个数据路径公开(公告)号：US06864892B2
公开(公告)日：2005-03-08
申请号：US10093835
申请日：2002-03-08
CPC分类号： G09G5/36 , G06T15/005
摘要： A system and method for preserving the order of data items through a divergence-and-reconvergence of two or more paths in a hardware device. A host processor may write a first token to a first path in the hardware device. A convergence unit in the hardware device may receive and store the first token in a synchronization register. The host processor may poll the synchronization register to determine when the first token arrives in the synchronization register. In response to determining that the first token has arrived in the synchronization register, the host processor may safely write a sequence of one or more data items to a second path in the hardware device.
摘要翻译： 一种用于通过硬件设备中两个或多个路径的发散和再聚合来保持数据项的顺序的系统和方法。 主处理器可以将第一令牌写入硬件设备中的第一路径。 硬件设备中的会聚单元可以将第一令牌接收并存储在同步寄存器中。 主处理器可以轮询同步寄存器以确定第一个令牌何时到达同步寄存器。 响应于确定第一令牌已经到达同步寄存器，主处理器可以安全地将一个或多个数据项的序列写入硬件设备中的第二路径。
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4.发明授权公开(公告)号：US06859209B2
公开(公告)日：2005-02-22
申请号：US09861468
申请日：2001-05-18
申请人： Michael G. Lavelle , Brian D. Emberling , Ranjit S. Oberoi , Deron D. Johnson , Ewa M. Kubalska
发明人： Michael G. Lavelle , Brian D. Emberling , Ranjit S. Oberoi , Deron D. Johnson , Ewa M. Kubalska
CPC分类号： G09G5/363 , G06T11/40 , G06T15/005
摘要： A graphics system applies multiple layers of texture information to triangles. The graphics system includes a hardware accelerator, a frame buffer and a video output processor. The hardware accelerator receives vertices of a triangle, identifies fragments of a sampling space which intersect the triangle, and applies the multiple layers of texture to the intersecting fragments. The multiple layers of textures may be stored in a texture memory external to the hardware accelerator. The hardware accelerator switches to a next texture layer after applying the textures of a current layer to all the fragments of the triangle. The hardware accelerator includes (or couples to) a texture accumulation buffer which stores color values associated with the triangle fragments between the application of successive texture layers. The frame buffer stores the samples and pixels generated from the samples by filtration. The video output processor transforms the pixels into a video signal.
摘要翻译： 图形系统将多层纹理信息应用于三角形。 图形系统包括硬件加速器，帧缓冲器和视频输出处理器。 硬件加速器接收三角形的顶点，识别与三角形相交的采样空间的片段，并将多层纹理应用于相交片段。 多层纹理可以存储在硬件加速器外部的纹理存储器中。 硬件加速器在将当前层的纹理应用于三角形的所有片段之后切换到下一个纹理层。 硬件加速器包括（或耦合到）纹理累积缓冲器，其存储与连续纹理层的应用之间的三角形片段相关联的颜色值。 帧缓冲器通过过滤存储从样本产生的样本和像素。 视频输出处理器将像素转换为视频信号。
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公开(公告)号：US06812928B2
公开(公告)日：2004-11-02
申请号：US10060978
申请日：2002-01-30
IPC分类号： G09G539
CPC分类号： G09G5/39 , G06T1/60 , G06T15/04 , G09G2320/0285 , G09G2360/122 , G09G2360/128
摘要： An optimizing unit for use with an interleaved memory and suitable for use in a computer graphics system is described. The unit utilizes knowledge of the repetitive and predictable nature of texture buffer accesses to potentially reduce the number of memory fetches. The unit maintains a queue of pending requests for tiles of data from the memory, and predicts the retrieval of redundant data within short sequences of requests. The redundant data is retrieved from the memory once, and repeated as necessary from local temporary storage registers.
摘要翻译： 描述了一种用于交错存储器并适用于计算机图形系统的优化单元。 该单元利用纹理缓冲器访问的重复性和可预测性质的知识来潜在地减少存储器提取的数量。 该单元维护来自存储器的数据块的待处理请求队列，并且预测在短序列请求内检索冗余数据。 冗余数据从存储器中检索一次，并根据需要从本地临时存储寄存器重复。
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公开(公告)号：US06847372B2
公开(公告)日：2005-01-25
申请号：US10094934
申请日：2002-03-11
CPC分类号： G06T15/04 , G06T15/005
摘要： A system and a method for improving magnified texture-mapped pixel performance in a single-pixel pipeline. Two textured pixel addresses corresponding to two pixels may be generated. The two textured pixel addresses may then be passed to the next unit in the pipeline, where the two textured pixel addresses can be examined if the corresponding two pixels correspond to a common set of texels in texture space. The two textured pixel addresses may be merged together if the two pixels correspond to the common set of texels. Merging may operate to create a combined texel structure. Texel data may be generated in response to receiving the combined texel structure. The texel data may be filtered using one or more texture filters in order to generate texture values.
摘要翻译： 一种用于改善单像素管道中放大的纹理映射像素性能的系统和方法。 可以生成对应于两个像素的两个纹理像素地址。 然后可以将两个纹理像素地址传递到流水线中的下一个单元，其中如果对应的两个像素对应于纹理空间中的一组公共的纹素，则可以检查两个纹理像素地址。 如果两个像素对应于公共的一组纹素，则两个纹理像素地址可以被合并在一起。 合并可以操作以创建组合的纹理结构。 可以响应于接收组合的纹素结构而生成Texel数据。 纹理数据可以使用一个或多个纹理滤波器进行滤波，以生成纹理值。
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7.发明授权公开(公告)号：US06778188B2
公开(公告)日：2004-08-17
申请号：US10085634
申请日：2002-02-28
IPC分类号： G09G500
CPC分类号： G06T15/005 , G06T5/20 , G06T15/04
摘要： A programmable filter comprising a tree of computational units, where each computational unit is configured to receive multiple inputs and generate multiple outputs, where the tree receives a set of input operands and generates output operands, where, in a sum of products mode, the output operands of the tree comprise a sum of products of the input operands by corresponding N-bit coefficients, where N is a positive integer, where, in a linear interpolation mode, each of the output operands of the tree comprise linear interpolations of at least two of the input operands, wherein coefficients of the linear interpolations have (N/2) bits of precision.
摘要翻译： 一种包括计算单元树的可编程滤波器，其中每个计算单元被配置为接收多个输入并产生多个输出，其中所述树接收一组输入操作数并产生输出操作数，其中，在产品模式之和中，输出 树的操作数包括相应的N位系数的输入操作数的乘积之和，其中N是正整数，其中，在线性内插模式中，树的每个输出操作数包括至少两个的线性内插 的输入操作数，其中线性内插的系数具有（N / 2）位精度。
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公开(公告)号：US07145570B2
公开(公告)日：2006-12-05
申请号：US10317599
申请日：2002-12-12
IPC分类号： G09G5/00
CPC分类号： G06T15/005 , G06T15/04
摘要： A system and a method for improving magnified texture-mapped pixel performance in a single-pixel pipeline. A plurality of textured pixel addresses corresponding to a plurality of pixels may be generated. A FIFO or other memory unit may be used to linearly order the plurality of textured pixel addresses. Two consecutive textured pixel addresses out of the plurality of textured pixel addresses may be examined if they map to a common set of texels in texture space. The two consecutive textured pixel addresses may be merged together and propagated down the pipeline if they map to the common set of texels. However, only a first of the two consecutive textured pixel addresses may be propagated down the pipeline if the two consecutive textured pixel addresses do not map to a common set of texels. Texel data may be generated in response to receiving either the combined texel structure or the first of the two textured pixel addresses. The texel data may be filtered using one or more texture filters in order to generate texture values. The next two textured pixel addresses that may be examined by the merge unit include the subsequent two consecutive textured pixel addresses, or a second of the two consecutive textured pixel addresses and a subsequent consecutive textured pixel address.
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公开(公告)号：US06906720B2
公开(公告)日：2005-06-14
申请号：US10096065
申请日：2002-03-12
CPC分类号： G06T1/60 , G06T11/40 , G09G5/363 , G09G5/39 , G09G2360/12
摘要： A graphics system may include a frame buffer, a processing device coupled to output data, a multipurpose memory device that includes a plurality of storage locations and is coupled to store data output from the processing device, and a multipurpose memory controller coupled to the multipurpose memory device. The multipurpose memory controller may be configured to allocate a first plurality of the storage locations to a first image buffer configured to store image data, a second plurality of the storage locations to a first texture buffer configured to store texture data, and a third plurality of the storage locations to a first accumulation buffer configured to store accumulation buffer data. The multipurpose memory device may be configured to include a first image buffer, a first texture buffer, and a first accumulation buffer at the same time.
摘要翻译： 图形系统可以包括帧缓冲器，耦合到输出数据的处理设备，包括多个存储位置并被耦合以存储从处理设备输出的数据的多用途存储器设备，以及耦合到多用途存储器的多用途存储器控制器 设备。 多用途存储器控制器可以被配置为将第一多个存储位置分配给被配置为存储图像数据的第一图像缓冲器，第二多个存储位置分配给被配置为存储纹理数据的第一纹理缓冲器，以及第三多个 存储位置到被配置为存储累积缓冲器数据的第一累积缓冲器。 多用途存储器装置可以被配置为同时包括第一图像缓冲器，第一纹理缓冲器和第一累积缓冲器。
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10.发明授权Early primitive assembly and screen-space culling for multiple chip graphics system 有权早期的原始装配和屏幕空间剔除多芯片图形系统公开(公告)号：US06943797B2
公开(公告)日：2005-09-13
申请号：US10611271
申请日：2003-06-30
CPC分类号： G06T15/005 , G06T1/60 , H04N19/42 , H04N19/80
摘要： A multi-chip system and method are disclosed for incorporating a primitive assembler in each of one or more geometry chips and one or more rasterization chips. This system may allow per-primitive operations to be performed in the geometry chips, and also allow use of a vertex data interface for sending vertex data to the rasterization chips. The primitive assemblers in the geometry chips may assemble vertices into primitives for clipping tests. The geometry chips may also test an assembled primitive against the projected boundaries of a set of screen space regions, where each region is assigned to one of the rasterization chips. Those primitives residing in more than one region may be sub-divided into two or more new primitives so that each new primitive resides in only one screen space region. The geometry chip may then send the vertex data for each primitive to the corresponding rasterization chip.
摘要翻译： 公开了一种用于将原始汇编器并入一个或多个几何码片和一个或多个光栅化码片的每一个中的多芯片系统和方法。 该系统可以允许在几何芯片中执行每个原始操作，并且还允许使用顶点数据接口将顶点数据发送到光栅化芯片。 几何芯片中的原始汇编器可以将顶点组装成用于剪切测试的基元。 几何芯片还可以针对一组屏幕空间区域的投影边界来测试组合的图元，其中每个区域被分配给光栅化芯片中的一个。 驻留在多个区域中的这些原语可以被细分为两个或更多个新的基元，使得每个新的基元仅驻留在一个屏幕空间区域。 然后，几何芯片可以将每个基元的顶点数据发送到相应的光栅化芯片。
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