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123 条记录 (耗时 0.027 秒)

    Flip-Flop Capable of Operating at High-Speed
    63.
    发明申请
    Flip-Flop Capable of Operating at High-Speed 审中-公开
    触发器能够高速运行

    公开(公告)号：US20090237137A1

    公开(公告)日：2009-09-24

    申请号：US12404982

    申请日：2009-03-16

    申请人： Min-Su Kim

    发明人： Min-Su Kim

    IPC分类号： H03K3/356 ,  H03K3/00

    CPC分类号： H03K3/35625 ,  H03K3/012 ,  H03K3/356121

    摘要： A flip-flop is provided for minimizing an input-output (D-Q) delay. The flip-flop includes a pull-up unit that receives a signal from a first node, is connected between a power voltage source and a second node, and pulls-up a voltage of the second node. A pull-down unit receives the signal from the first node, is connected between a ground voltage source and the second node, and pulls-down the voltage of the second node. A latch unit is connected to the second node and latches and outputs a signal transferred to the second node. The pull-up unit pulls-up the second node in response to one of a clock signal and a pulse signal, and the pull-down unit pulls-down the second node in response to the other one of the clock signal and the pulse signal.

    摘要翻译： 提供了一种用于最小化输入输出（D-Q）延迟的触发器。 触发器包括从第一节点接收信号的上拉单元，连接在电源电压源和第二节点之间，并且上拉第二节点的电压。 下拉单元接收来自第一节点的信号，连接在地电压源和第二节点之间，并且拉下第二节点的电压。 锁存单元连接到第二节点并锁存并输出传送到第二节点的信号。 上拉单元响应于时钟信号和脉冲信号中的一个上拉第二节点，并且下拉单元响应于另一个时钟信号和脉冲信号而拉下第二节点 。

    PULSE OPERATED FLIP-FLOP CIRCUIT HAVING TEST-INPUT FUNCTION AND ASSOCIATED METHOD
    64.
    发明申请
    PULSE OPERATED FLIP-FLOP CIRCUIT HAVING TEST-INPUT FUNCTION AND ASSOCIATED METHOD 有权
    具有测试输入功能和相关方法的脉冲操作FLIP-FLOP电路

    公开(公告)号：US20090115481A1

    公开(公告)日：2009-05-07

    申请号：US12256244

    申请日：2008-10-22

    申请人： Min-Su Kim

    发明人： Min-Su Kim

    IPC分类号： H03K3/00 ,  H03K3/02

    CPC分类号： G01R31/31858 ,  G01R31/318594

    摘要： The pulse generation circuit generates a first pulse signal and a complementary second pulse signal. The first and second pulse signals are activated simultaneously in a normal mode and activated selectively in response to a test input signal in a test mode. A multiplexing input circuit selects and outputs one of a data input signal and a test input signal as a latch input signal in response to the first pulse signal and the second pulse signal. The latch input signal corresponds to the data input signal in the normal mode and corresponds to the test input signal in the test mode. The latching circuit latches the latch input signal to generate data output signal. The length of data transfer path is reduced, and DtoQ delay can be decreased.

    摘要翻译： 脉冲发生电路产生第一脉冲信号和互补的第二脉冲信号。 第一和第二脉冲信号在正常模式下同时被激活并且响应于测试模式下的测试输入信号而被选择性地激活。 复用输入电路响应于第一脉冲信号和第二脉冲信号，选择并输出数据输入信号和测试输入信号中的一个作为锁存输入信号。 锁存输入信号对应于正常模式下的数据输入信号，对应于测试模式下的测试输入信号。 锁存电路锁存锁存器输入信号以产生数据输出信号。 减少数据传输路径的长度，减少DtoQ延迟。

    Gated clock logic circuit
    65.
    发明授权
    Gated clock logic circuit 有权
    门控时钟逻辑电路

    公开(公告)号：US07365575B2

    公开(公告)日：2008-04-29

    申请号：US11266659

    申请日：2005-11-02

    申请人： Min-Su Kim

    发明人： Min-Su Kim

    IPC分类号： H03K19/096

    CPC分类号： G06F1/04 ,  G06F1/3237 ,  H03K3/012 ,  H03K3/356121 ,  H03K5/135 ,  Y02D10/128

    摘要： A gated clock logic circuit includes a pulse generator and a precharged latch. The pulse generator generates a pulse signal in response to a clock signal, and the precharged latch generates a gated clock signal in response to the clock signal, the pulse signal, and a control signal.

    摘要翻译： 门控时钟逻辑电路包括脉冲发生器和预充电锁存器。 脉冲发生器响应于时钟信号产生脉冲信号，并且预充电锁存器响应于时钟信号，脉冲信号和控制信号产生门控时钟信号。

    Voltage conversion circuit with stable transition delay characteristic
    66.
    发明授权
    Voltage conversion circuit with stable transition delay characteristic 有权
    具有稳定转换延迟特性的电压转换电路

    公开(公告)号：US07355446B2

    公开(公告)日：2008-04-08

    申请号：US11429175

    申请日：2006-05-05

    申请人： Min-Su Kim

    发明人： Min-Su Kim

    IPC分类号： H03K19/0175

    CPC分类号： H03K19/00323 ,  H03K3/011 ,  H03K3/0375 ,  H03K3/356113

    摘要： A voltage conversion circuit changes an input signal of a first voltage into an output signal of a second voltage. The circuit includes an input terminal receiving an input signal, an output terminal generating an output signal, and first and second level-shifting units connected in parallel between the input and output terminals. The first and second level-shifting units have different transition delay characteristics, enabling rising and falling transition delays to be variable in the same ratio when the first and second voltages are changed.

    摘要翻译： 电压转换电路将第一电压的输入信号改变为第二电压的输出信号。 电路包括接收输入信号的输入端子，产生输出信号的输出端子以及在输入和输出端子之间并联连接的第一和第二电平移动单元。 第一和第二电平移位单元具有不同的转变延迟特性，使得当第一和第二电压改变时，上升和下降转换延迟可以以相同的比例变化。

    Organic electroluminescent display device and method of fabricating the same
    67.
    发明申请
    Organic electroluminescent display device and method of fabricating the same 有权
    有机电致发光显示装置及其制造方法

    公开(公告)号：US20070285007A1

    公开(公告)日：2007-12-13

    申请号：US11600904

    申请日：2006-11-17

    申请人： Byoung-June Lee ,  Nho-Hoon Myoung ,  Min-Su Kim

    发明人： Byoung-June Lee ,  Nho-Hoon Myoung ,  Min-Su Kim

    IPC分类号： H01L51/50 ,  H01J9/00

    CPC分类号： H01L27/3251 ,  H01L51/524 ,  H01L51/5246 ,  H01L51/525

    摘要： An organic electroluminescent display (OELD) device includes first and second substrates facing each other and having a display region and a non-display region on a periphery of the display region, an organic electroluminescent diode in the display region of the first substrate, a protrusion formed with a first thickness and a first width in the non-display region of the first substrate, a groove formed with a first depth and a second width in the non-display region of the second substrate, wherein the protrusion is inserted into the groove, a seal pattern formed between the protrusion and the groove.

    摘要翻译： 有机电致发光显示器（OELD）器件包括彼此面对的第一和第二基板，并且在显示区域的周围具有显示区域和非显示区域，第一基板的显示区域中的有机电致发光二极管， 在所述第一基板的非显示区域中形成有第一厚度和第一宽度，在所述第二基板的非显示区域中形成有第一深度和第二宽度的凹槽，其中所述突起插入所述凹槽中 ，形成在突起和槽之间的密封图案。

    Caller ID mobile terminal
    68.
    发明申请
    Caller ID mobile terminal 审中-公开
    来电显示移动终端

    公开(公告)号：US20070123234A1

    公开(公告)日：2007-05-31

    申请号：US11540731

    申请日：2006-10-02

    申请人： Min-Su Kim

    发明人： Min-Su Kim

    IPC分类号： H04Q7/38 ,  H04Q7/22 ,  H04M3/42

    CPC分类号： H04M1/578 ,  H04M1/576 ,  H04M1/72563 ,  H04M19/041

    摘要： Disclosed is a caller ID mobile terminal which allows a user to exactly identify a caller. The user can exactly recognize the caller as voices directly recorded and stored by the user by individual or voices reading nicknames entered in text ring as bell tones, and further the user can be amused by using various versions of voices as bell tones through emoticons or the like.

    摘要翻译： 公开了一种主叫用户ID移动终端，其允许用户精确地识别呼叫者。 用户可以将呼叫者精确地识别为用户通过个人或声音读取以文本形式输入的昵称作为铃声直接记录和存储的语音，并且还可以通过使用各种语音作为铃声通过表情符号或 喜欢。

    Pulse-based flip-flop
    69.
    发明授权
    Pulse-based flip-flop 有权

    公开(公告)号：US07202724B2

    公开(公告)日：2007-04-10

    申请号：US10997958

    申请日：2004-11-29

    申请人： Min-Su Kim

    发明人： Min-Su Kim

    IPC分类号： H03K3/286 ,  H03K3/356 ,  H03K3/00 ,  G06F1/04

    CPC分类号： H03K5/151 ,  H03K3/037 ,  H03K5/135 ,  H03K5/1534

    摘要： A pulse-based flip-flop that latches a data input signal to convert the data input signal into a data output signal in response to a clock signal. The pulse-based flip-flop comprises a latch that latches the data input signal in response to a first clock pulse signal and a second clock pulse signal and a pulse generator including a NAND gate, a variable delay, and a first inverter, the pulse generator receives the clock signal to generate the first clock pulse signal and the second clock pulse signal. The NAND gate receives the clock signal and an output signal of the variable delay and outputs the second clock pulse signal. The first inverter receives the first clock pulse signal and outputs the second clock pulse signal. The variable delay receives the clock signal and the second clock pulse, and an output signal of the variable delay feeds back to the NAND gate.

    Level shifter and method thereof
    70.
    发明申请
    Level shifter and method thereof 审中-公开
    电平移位器及其方法

    公开(公告)号：US20060290405A1

    公开(公告)日：2006-12-28

    申请号：US11471624

    申请日：2006-06-21

    申请人： Min-Su Kim ,  Young-Min Shin

    发明人： Min-Su Kim ,  Young-Min Shin

    IPC分类号： H03L5/00

    CPC分类号： H03K3/35613

    摘要： A level shifter and method thereof. The example level shifter may include a level shifting unit generating a plurality of internal voltages, shifting the voltage levels of a plurality of input signals and outputting an output signal based at least in part on the plurality of internal voltages and a mode control unit controlling the voltage levels of the plurality of internal voltages in response to a mode selection signal. The example method may include generating a plurality of internal voltages based on a plurality of input signals, controlling the voltage levels of the plurality of internal voltages based on a mode selection signal and outputting an output signal based at least in part on the plurality of internal voltages.

    摘要翻译： 一种电平转换器及其方法。 示例电平移位器可以包括产生多个内部电压的电平移位单元，至少部分地基于多个内部电压来移位多个输入信号的电压电平并输出输出信号，以及模式控制单元控制 响应于模式选择信号，多个内部电压的电压电平。 该示例性方法可以包括基于多个输入信号生成多个内部电压，基于模式选择信号来控制多个内部电压的电压电平，并且至少部分地基于多个内部电压输出输出信号 电压。