公开(公告)号：US11206410B2

公开(公告)日：2021-12-21

申请号：US17031087

申请日：2020-09-24

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Ryuichi Kanoh

IPC: H04N19/159 ,  H04N19/105 ,  H04N19/176 ,  H04N19/186 ,  H04N19/583

Abstract: An encoder includes memory, and circuitry accessible to the memory. The circuitry accessible to the memory: determines whether OBMC is applicable to generation of a prediction image of a current block, according to whether BIO is to be applied to the generation of the prediction image of the current block; when BIO is to be applied to the generation of the prediction image of the current block, determines that OBMC is not applicable to the generation of the prediction image of the current block, and applies BIO to the generation of the prediction image of the current block without applying OBMC.

公开(公告)号：US11166026B2

公开(公告)日：2021-11-02

申请号：US16192070

申请日：2018-11-15

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Takahiro Nishi ,  Tadamasa Toma ,  Kiyofumi Abe

IPC: H04N19/13 ,  H04N19/70 ,  H04N19/172 ,  H04N19/174 ,  H04N19/91 ,  H04N19/124 ,  H04N19/159

Abstract: An encoder is an encoder which encodes image information and includes memory and circuitry accessible to the memory. The circuitry derives, from the image information, a binary data string according to binarization for arithmetic encoding, and outputs a bit stream including the binary data string and application information indicating whether or not the binary data string has been arithmetic encoded. The circuitry outputs, as the bit stream, a string including as the binary data string, a data string which has not been arithmetic encoded; and, as the application information, information indicating that the binary data string has not been arithmetic encoded.

公开(公告)号：US11146811B2

公开(公告)日：2021-10-12

申请号：US16682749

申请日：2019-11-13

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Ryuichi Kanoh

IPC: H04N19/537 ,  H04N19/105 ,  H04N19/157 ,  H04N19/52 ,  H04N19/573

Abstract: An encoder includes memory and circuitry. The circuitry: derives a first motion vector in a unit of a prediction block using a first inter frame prediction mode that uses a degree of matching between two reconstructed images of two regions in two difference pictures, the prediction block being obtained by splitting an image included in a video; and performs, in the unit of the prediction block, a first motion compensation process that generates a prediction image by referring to a spatial gradient of luminance in an image generated by performing motion compensation using the first motion vector derived.

公开(公告)号：US11115654B2

公开(公告)日：2021-09-07

申请号：US16901869

申请日：2020-06-15

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Ryuichi Kanoh

IPC: H04N19/119 ,  H04N19/105 ,  H04N19/139 ,  H04N19/14 ,  H04N19/176 ,  H04N19/52 ,  H04N19/573

Abstract: An encoder is disclosed which includes circuitry and memory. Using the memory, the circuitry, in a first operating mode, derives first motion vectors for a first block obtained by splitting a picture, and generates a prediction image corresponding to the first block, with a bi-directional optical flow flag settable to true, and by referring to spatial gradients of luminance generated based on the first motion vectors. Using the memory, the circuitry, in a second operating mode, derives second motion vectors for a sub-block obtained by splitting a second block, the second block being obtained by splitting the picture, and generates a prediction image corresponding to the sub-block, with the bi-directional optical flow flag set to false.

公开(公告)号：US11102472B2

公开(公告)日：2021-08-24

申请号：US16845322

申请日：2020-04-10

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi Abe ,  Kazuhito Kimura ,  Hideyuki Ohgose ,  Hiroshi Arakawa ,  Koji Arimura

IPC: H04B1/66 ,  H04N7/12 ,  H04N11/02 ,  H04N11/04 ,  H04N19/102 ,  H04N19/172 ,  H04N19/46 ,  H04N19/112 ,  H04N19/16 ,  H04N19/70 ,  H04N19/61 ,  H04N19/577

Abstract: A video decoding device, in the case where a video of the progressive format is inputted, processes a frame as a picture, in the case where a video of the interlace format is inputted, processes a field as a picture. A video decoding device performs display control corresponding to a format of the both video by analyzing display control information in display control information analyzer. The display control information includes sequence unit display control information which is commonly used in a display process of all pictures that belong to a sequence to be decoded and picture unit display control information which is individually used in a display process of a picture to be decoded. A second code string analyzer acquires each of the sequence unit display control information and the picture unit display control information from an extended information area in units of pictures.

公开(公告)号：US11095883B2

公开(公告)日：2021-08-17

申请号：US17173634

申请日：2021-02-11

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Tadamasa Toma ,  Takahiro Nishi ,  Kiyofumi Abe ,  Yusuke Kato

IPC: H04N19/105 ,  H04N19/176 ,  H04N19/182

Abstract: An encoder includes circuitry and memory connected to the circuitry. The circuitry, in operation: derives, as a first parameter, a total sum of absolute values of sums of horizontal gradient values respectively for pairs of relative pixel positions; derives, as a second parameter, a total sum of absolute values of sums of vertical gradient values respectively for the pairs of relative pixel positions; derives, as a third parameter, a total sum of horizontal-related pixel difference values respectively for the pairs of relative pixel positions; derives, as a fourth parameter, a total sum of vertical-related pixel difference values respectively for the pairs of relative pixel positions; derives, as a fifth parameter, a total sum of vertical-related sums of horizontal gradient values respectively for the pairs of relative pixel positions; and generates a prediction image to be used to encode the current block using the first, second, third, fourth, and fifth parameters.

公开(公告)号：US11070837B2

公开(公告)日：2021-07-20

申请号：US16371691

申请日：2019-04-01

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Ryuichi Kanoh ,  Tadamasa Toma ,  Kiyofumi Abe ,  Takahiro Nishi

IPC: H04N19/176 ,  H04N19/124 ,  H04N19/122 ,  H04N19/52 ,  H04N19/44

Abstract: An encoder includes circuitry and memory. Using the memory, the circuitry performs a primary transform on a derived prediction error, performs a secondary transform on a result of the primary transform, quantizes a result of the secondary transform, and encodes a result of the quantization as data of an image. When a current block to be processed has a predetermined shape, the encoder performs the secondary transform using, among secondary transform basis candidates that are secondary bases usable in the secondary transform, only a secondary transform basis candidate having a size that is not largest size containable in the current block.

公开(公告)号：US11044491B2

公开(公告)日：2021-06-22

申请号：US16942601

申请日：2020-07-29

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Ryuichi Kanoh ,  Chong Soon Lim ,  Ru Ling Liao ,  Hai Wei Sun ,  Sughosh Pavan Shashidhar ,  Han Boon Teo ,  Jing Ya Li

IPC: H04N11/02 ,  H04N19/52 ,  H04N19/119 ,  H04N19/176

Abstract: Provided is an encoder which includes circuitry and memory. Using the memory, the circuitry splits an image block into a plurality of partitions, obtains a prediction image for a partition, and encodes the image block using the prediction image. When the partition is not a non-rectangular partition, the circuitry obtains (i) a first prediction image for the partition using a first motion vector for the partition, (ii) a second motion vector for the partition using the first prediction image, and (iii) a second prediction image for the partition as the prediction image using the second motion vector. When the partition is a non-rectangular partition, the circuitry obtains the first prediction image as the prediction image using the first motion vector, without using the second motion vector.

公开(公告)号：US11044476B2

公开(公告)日：2021-06-22

申请号：US17087128

申请日：2020-11-02

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Tadamasa Toma ,  Takahiro Nishi ,  Kiyofumi Abe ,  Ryuichi Kanoh ,  Chong Soon Lim ,  Sughosh Pavan Shashidhar ,  Ru Ling Liao ,  Hai Wei Sun ,  Han Boon Teo ,  Jing Ya Li

IPC: H04N19/96 ,  H04N19/176 ,  H04N19/119 ,  H04N19/157

Abstract: An encoder partitions into blocks using a set of block partition modes. The set of block partition modes includes a first partition mode for partitioning a first block, and a second block partition mode for partitioning a second block which is one of blocks obtained after the first block is partitioned. When the number of partitions of the first block partition mode is three, the second block is a center block among the blocks obtained after partitioning the first block, and the partition direction of the second block partition mode is same as the partition direction of the first block partition mode, the second block partition mode indicates that the number of partitions is only three. A parameter for identifying the second block partition mode includes a first flag indicating a horizontal or vertical partition direction, and does not include a second flag indicating the number of partitions.

公开(公告)号：US10812793B2

公开(公告)日：2020-10-20

申请号：US16726370

申请日：2019-12-24

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Ryuichi Kanoh

IPC: H04N19/105 ,  H04N19/159 ,  H04N19/176 ,  H04N19/186

Abstract: An encoder includes memory and circuitry. The circuitry, using the memory, (i) selects a mode from among a plurality of modes each for deriving a motion vector, and derives a motion vector for a current block via the selected mode, and (ii) performs inter prediction encoding on the current block, using the derived motion vector, via one of a skip mode and a non-skip mode different from the skip mode. The plurality of modes include a plurality of first modes each for predicting the motion vector for the current block based on an encoded block neighboring the current block without encoding information indicating a motion vector into a stream. When a second mode included in the plurality of first modes is selected, the current block is encoded via the non-skip mode regardless of presence or absence of a residual coefficient.