MMIC driver amplifier having zig-zag RF signal flow

    公开(公告)号:US06664855B2

    公开(公告)日:2003-12-16

    申请号:US10118277

    申请日:2002-04-08

    IPC分类号: H03F360

    CPC分类号: H03F3/195 H03F3/211

    摘要: A MMIC (microwave monolithic integrated circuit) driver amplifier having a zig-zag RF signal flow and method for the same is provided. A smaller die size and higher output gain are realized with the improved amplification stage geometry provided herein. In particular, the stages are configured in a “stacked” topology permitting a zig-zag RF signal flow through the stages. Additionally, the DC bias circuitry may be is centralized and adjacent stages may share vias. The die area for a typical K-band driver amplifier may be reduced by about 56% over a conventional amplifier design.

    MMIC folded power amplifier
    62.
    发明授权
    MMIC folded power amplifier 有权
    MMIC折叠功率放大器

    公开(公告)号:US06359515B1

    公开(公告)日:2002-03-19

    申请号:US09832590

    申请日:2001-04-11

    申请人: Kenneth V. Buer

    发明人: Kenneth V. Buer

    IPC分类号: H03F368

    摘要: A MMIC (microwave monolithic integrated circuit) power amplifier and method for the same is provided. A smaller die size and higher power output are realized with the improved amplifier and transistor geometry herein provided. In particular, transistors, such as FETs (field effect transistors) are displaced from a conventional FET geometry with alternating FETs being rotated in opposite directions. The inputs (gate pads) and outputs (drain pads) of two adjacent FETs may be “shared.” The improved FET configuration reduces the number of splitting and combining networks by up to 50% over the prior art and the die area for a typical 4 watt power amplifier is reduced by 48-72% over the prior art. The improved amplifier configuration provides a multi-sectional configuration wherein one section may be the mirrored image of another. In a two section amplifier, the amplifier appears to be “folded.”

    摘要翻译: 提供了一种MMIC(微波单片集成电路)功率放大器及其方法。 利用本文提供的改进的放大器和晶体管几何结构实现更小的管芯尺寸和更高的功率输出。 特别地,诸如FET(场效应晶体管)的晶体管从传统的FET几何形状中移位,交变的FET沿相反方向旋转。 两个相邻FET的输入(栅极焊盘)和输出(漏极焊盘)可以“共享”。 改进的FET配置将分离和组合网络的数量减少了高达现有技术的50%,并且典型的4瓦功率放大器的管芯面积比现有技术减少了48-72%。 改进的放大器配置提供多截面配置,其中一个部分可以是另一部分的镜像。 在两段放大器中,放大器似乎是“折叠的”。

    Efficient solid-state high frequency power amplifier structure
    63.
    发明授权
    Efficient solid-state high frequency power amplifier structure 有权
    高效率固态高频功率放大器结构

    公开(公告)号:US6160454A

    公开(公告)日:2000-12-12

    申请号:US175037

    申请日:1998-10-19

    IPC分类号: H01P5/12 H03F3/68 H03F3/14

    CPC分类号: H01P5/12

    摘要: A power amplifier uses a plurality of solid-state amplifiers (FIGS. 2 and 3, 140) arranged in a parallel manner to form a power amplifier module (10). Each solid-state amplifier is adhered to a low thermal expansion insert (130). The insert is then coupled to a low cost aluminum substrate in order to carry the excess heat from each solid-state amplifier (140) to the aluminum housing. The power outputs from the solid-state amplifiers from each module are combined with the power outputs from other modules using electroformed waveguide combiners (FIG. 1, 30, 40).

    摘要翻译: 功率放大器使用以并行方式布置的多个固态放大器(图2和3,140)以形成功率放大器模块(10)。 每个固态放大器粘附到低热膨胀插入件(130)上。 然后将插入件耦合到低成本的铝基板,以便将来自每个固态放大器(140)的多余的热量运送到铝外壳。 来自每个模块的固态放大器的功率输出与使用电铸波导组合器的其它模块的功率输出组合(图1,30,40)。

    Method and apparatus for power combining/dividing
    64.
    发明授权
    Method and apparatus for power combining/dividing 失效
    功率组合/分割的方法和装置

    公开(公告)号:US5576671A

    公开(公告)日:1996-11-19

    申请号:US427323

    申请日:1995-04-24

    IPC分类号: H01P5/12

    CPC分类号: H01P5/12

    摘要: A method and apparatus for power combining or dividing handles high impedance line requirements in n-way combiners (15) and dividers (10) using phase delay networks (12, 14) to transform impedances to a lower, intermediate impedance. Each impedance transformation is accomplished using a stepped impedance or tapered impedance transmission line (26). The method and apparatus provides isolation between input or output ports (11, 22 and 24, 13) in power combining or dividing circuits using an incremental phase delay network (12) of prescribed electrical phase lengths (22, 24) to provide phase cancellation. The power divider (10) and combiner (15) can be used in power amplifiers and in communication devices.

    摘要翻译: 用于功率组合或分频的方法和装置利用相位延迟网络(12,14)处理n路组合器(15)和分频器(10)中的高阻抗线路要求,以将阻抗变换到较低的中间阻抗。 使用阶梯式阻抗或锥形阻抗传输线(26)来实现每个阻抗变换。 该方法和装置在使用规定电相位长度(22,24)的增量相位延迟网络(12)进行功率组合或分频的输入或输出端口(11,22和24,13)之间提供隔离以提供相位消除。 功率分配器(10)和组合器(15)可用于功率放大器和通信设备中。

    Active General Purpose Hybrid
    65.
    发明申请
    Active General Purpose Hybrid 有权
    主动通用混合动力

    公开(公告)号:US20130136209A1

    公开(公告)日:2013-05-30

    申请号:US13306937

    申请日:2011-11-29

    IPC分类号: H04L27/00

    CPC分类号: H04L27/365 H04L27/362

    摘要: A general purpose hybrid includes a first input port in communication with a first dual vector generator, a second input port in communication with a second dual vector generator, a first active combiner receives a first signal from the first dual vector generator and a third signal from the second dual vector generator, where the first and second dual vector generators independently apply phase shifting and amplitude control to the first and third signals; a second active combiner receives a second signal from the first dual vector generator and a fourth signal from the second dual vector generator, where the first and second dual vector generators independently apply phase shifting and amplitude control to the second and fourth signals; a first output port provides a first composite signal from the first active combiner; and a second output port provides a second composite signal from the second active combiner.

    摘要翻译: 通用混合动力车包括与第一双向量发生器通信的第一输入端口,与第二双向量发生器通信的第二输入端口,第一有源组合器从第一双向量发生器接收第一信号,以及从第一双向量发生器接收第三信号, 第二双矢量发生器,其中第一和第二双矢量发生器独立地对第一和第三信号施加相移和幅度控制; 第二有源组合器从第一双向量发生器接收第二信号和从第二双向量发生器接收第四信号,其中第一和第二双向量发生器独立地对第二和第四信号施加相移和幅度控制; 第一输出端口提供来自第一有源组合器的第一复合信号; 并且第二输出端口提供来自第二有源组合器的第二复合信号。

    Active phased array architecture
    66.
    发明授权
    Active phased array architecture 有权
    有源相控阵列架构

    公开(公告)号:US08410980B2

    公开(公告)日:2013-04-02

    申请号:US13540394

    申请日:2012-07-02

    IPC分类号: H01Q3/00

    摘要: In an exemplary embodiment, a phased array solid-state architecture has dual-polarized feeds and is manufactured, for example, on highly flexible silicon germanium (SiGe). The implementation of dual-polarized feeds facilitates the operation of phased arrays where the polarization can be statically or dynamically controlled on a subarray or element basis. In an exemplary embodiment, the sub-component control is configured to optimize a performance characteristic associated with polarization, such as phase or amplitude adjustment. An active phased array architecture may replace traditional distributed and GaAs implementations for the necessary functions required to operate electronically steerable phased array antennas. The architecture combines active versions of vector generators, power splitters, power combiners, and RF hybrids in a novel fashion to realize a fully or substantially monolithic solution for a wide range of antenna applications that can be realized with radiating elements having single-polarized or dual-polarized feeds.

    摘要翻译: 在示例性实施例中,相控阵列固态架构具有双极化馈电,并且例如在高度柔性的硅锗(SiGe)上制造。 双极化馈电的实现有助于相位阵列的操作,其中极化可以基于子阵列或元件静态或动态地控制。 在示例性实施例中,子部件控制被配置为优化与偏振相关联的性能特性,例如相位或幅度调整。 有源相控阵架构可以代替传统的分布式和GaAs实现,用于操作电子可控相控阵列天线所需的必要功能。 该架构以新颖的方式结合了矢量发生器,功率分配器,功率组合器和RF混合器的主动版本,以实现宽范围的天线应用的完全或基本上单片解决方案,可通过具有单极化或双重 极化饲料

    COMPACT HIGH LINEARITY MMIC BASED FET RESISTIVE MIXER
    67.
    发明申请
    COMPACT HIGH LINEARITY MMIC BASED FET RESISTIVE MIXER 有权
    紧凑的高线性MMIC基FET电阻式混频器

    公开(公告)号:US20110248766A1

    公开(公告)日:2011-10-13

    申请号:US12756955

    申请日:2010-04-08

    申请人: Kenneth V. Buer

    发明人: Kenneth V. Buer

    IPC分类号: G06G7/16

    摘要: A MMIC (microwave monolithic integrated circuit) based FET mixer and method for the same is provided. In particular, adjacent transistors, such as FETs (field effect transistors) share terminals reducing physical layout separation and interconnections. A smaller die size is realized with the improved system geometry herein provided.

    摘要翻译: 提供了一种基于MMIC(微波单片集成电路)的FET混频器及其方法。 特别地,诸如FET(场效应晶体管)的相邻晶体管共享终端,从而减少物理布局分离和互连。 使用本文提供的改进的系统几何形状实现较小的模具尺寸。

    Power efficient multistage amplifier and design method
    69.
    发明授权
    Power efficient multistage amplifier and design method 有权
    高效多级放大器和设计方法

    公开(公告)号:US07948324B2

    公开(公告)日:2011-05-24

    申请号:US12538437

    申请日:2009-08-10

    IPC分类号: H03F3/68

    CPC分类号: H03F3/189 H03F1/02

    摘要: A multistage amplifier and design method are disclosed. The multistage amplifier has a plurality of amplifier stages, each stage having an amplifier designed and biased to operate at or near the amplifier's power added efficiency (PAE) peak. The PAE peak of each of the amplifier is at or near the amplifiers linear-compression transition region, providing a multistage power amplifier that is power efficient and has desirable amplitude to amplitude and amplitude to phase power transfer characteristics. The amplifier is designed by matching the output impedance of a final stage with a load. Amplifier stages are iteratively designed from the last stage to the first. At each stage, an amplifier and drive circuit are designed. The drive circuit and amplifier are designed to provide each stage with output impedance matched to the input impedance of the following stage and to operate at or near the PAE peak of the amplifier.

    摘要翻译: 公开了一种多级放大器和设计方法。 多级放大器具有多个放大器级,每级具有设计和偏置以在放大器的功率增加效率(PAE)峰值附近操作的放大器。 每个放大器的PAE峰值处于或靠近放大器线性压缩过渡区域,提供功率有效的多级功率放大器,并具有期望的振幅和幅度与相位功率传输特性。 放大器的设计是通过匹配最后一级的输出阻抗与负载。 从最后阶段到第一阶段迭代设计放大器级。 在每个阶段,设计放大器和驱动电路。 驱动电路和放大器被设计成为每个级提供与下一级的输入阻抗匹配的输出阻抗,并在放大器的PAE峰值处或附近工作。

    ACTIVE PHASED ARRAY ARCHITECTURE
    70.
    发明申请
    ACTIVE PHASED ARRAY ARCHITECTURE 有权
    主动平面架构

    公开(公告)号:US20100259445A1

    公开(公告)日:2010-10-14

    申请号:US12759130

    申请日:2010-04-13

    IPC分类号: H01Q3/00

    摘要: In an exemplary embodiment, a phased array solid-state architecture has dual-polarized feeds and is manufactured, for example, on highly flexible silicon germanium (SiGe). The implementation of dual-polarized feeds facilitates the operation of phased arrays where the polarization can be statically or dynamically controlled on a subarray or element basis. In an exemplary embodiment, the sub-component control is configured to optimize a performance characteristic associated with polarization, such as phase or amplitude adjustment. An active phased array architecture may replace traditional distributed and GaAs implementations for the necessary functions required to operate electronically steerable phased array antennas. The architecture combines active versions of vector generators, power splitters, power combiners, and RF hybrids in a novel fashion to realize a fully or substantially monolithic solution for a wide range of antenna applications that can be realized with radiating elements having single-polarized or dual-polarized feeds.

    摘要翻译: 在示例性实施例中,相控阵列固态架构具有双极化馈电,并且例如在高度柔性的硅锗(SiGe)上制造。 双极化馈电的实现有助于相位阵列的操作,其中极化可以基于子阵列或元件静态或动态地控制。 在示例性实施例中,子部件控制被配置为优化与偏振相关联的性能特性,例如相位或幅度调整。 有源相控阵架构可以代替传统的分布式和GaAs实现,用于操作电子可控相控阵列天线所需的必要功能。 该架构以新颖的方式结合了矢量发生器,功率分配器,功率组合器和RF混合器的主动版本,以实现宽范围的天线应用的完全或基本上单片解决方案,可通过具有单极化或双重 极化饲料