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公开(公告)号：US07627735B2
公开(公告)日：2009-12-01
申请号：US11255676
申请日：2005-10-21
申请人： Roger Espasa , Joel Emer , Geoff Lowney , Roger Gramunt , Santiago Galan , Toni Juan , Jesus Corbal , Federico Ardanaz , Isaac Hernandez
发明人： Roger Espasa , Joel Emer , Geoff Lowney , Roger Gramunt , Santiago Galan , Toni Juan , Jesus Corbal , Federico Ardanaz , Isaac Hernandez
IPC分类号： G06F15/16
CPC分类号： G06F12/1027 , G06F12/0844 , Y02D10/13
摘要： In one embodiment, the present invention includes an apparatus having a register file to store vector data, an address generator coupled to the register file to generate addresses for a vector memory operation, and a controller to generate an output slice from one or more slices each including multiple addresses, where the output slice includes addresses each corresponding to a separately addressable portion of a memory. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明包括具有用于存储矢量数据的寄存器文件的装置，耦合到寄存器文件以产生矢量存储器操作的地址的地址发生器，以及控制器，用于从一个或多个片段生成输出片段 包括多个地址，其中输出切片包括各自对应于存储器的单独可寻址部分的地址。 描述和要求保护其他实施例。
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公开(公告)号：US09792115B2
公开(公告)日：2017-10-17
申请号：US13976997
申请日：2011-12-23
CPC分类号： G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30036 , G06F9/30145 , G06F9/3893
摘要： A processing core is described having execution unit logic circuitry having a first register to store a first vector input operand, a second register to a store a second vector input operand and a third register to store a packed data structure containing scalar input operands a, b, c. The execution unit logic circuitry further include a multiplier to perform the operation (a*(first vector input operand))+(b*(second vector operand))+c.
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公开(公告)号：US20140052968A1
公开(公告)日：2014-02-20
申请号：US13976404
申请日：2011-12-23
IPC分类号： G06F9/30
CPC分类号： G06F9/3001 , G06F9/30018 , G06F9/30036 , G06F9/30101 , G06F9/30145
摘要： A method of processing an instruction is described that includes fetching and decoding the instruction. The instruction has separate destination address, first operand source address and second operand source address components. The first operand source address identifies a location of a first mask pattern in mask register space. The second operand source address identifies a location of a second mask pattern in the mask register space. The method further includes fetching the first mask pattern from the mask register space; fetching the second mask pattern from the mask register space; merging the first and second mask patterns into a merged mask pattern; and, storing the merged mask pattern at a storage location identified by the destination address.
摘要翻译： 描述了处理指令的方法，其包括获取和解码指令。 该指令具有单独的目标地址，第一个操作数源地址和第二个操作数源地址组件。 第一个操作数源地址标识掩码寄存器空间中第一个掩码模式的位置。 第二操作数源地址在掩码寄存器空间中标识第二掩码图案的位置。 该方法还包括从掩模寄存器空间获取第一掩模图案; 从掩模寄存器空间中取出第二掩模图案; 将第一和第二掩模图案合并成合并的掩模图案; 以及将合并的掩模图案存储在由目的地地址识别的存储位置。
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64.发明申请Systems, Apparatuses, and Methods for Performing a Shuffle and Operation (Shuffle-Op) 有权用于执行随机播放和操作的系统，设备和方法（随机播放）公开(公告)号：US20140006756A1
公开(公告)日：2014-01-02
申请号：US13539116
申请日：2012-06-29
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F9/3001 , G06F9/30029 , G06F9/30032 , G06F9/30098 , G06F9/30145 , G06F9/3016
摘要： Embodiments of systems, apparatuses, and methods for performing in a computer processor a data element shuffle and an operation on the shuffled data elements in response to a single data element shuffle and an operation instruction that includes a destination vector register operand, a first and second source vector register operands, an immediate value, and an opcode are described.
摘要翻译： 用于在计算机处理器中响应于单个数据元素随机播放的数据元素随机播放和对混洗数据元素的操作的系统，装置和方法的实施例，以及包括目的地向量寄存器操作数，第一和第二 描述源向量寄存器操作数，立即值和操作码。
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公开(公告)号：US08316216B2
公开(公告)日：2012-11-20
申请号：US12582829
申请日：2009-10-21
申请人： Roger Espasa , Joel Emer , Geoff Lowney , Roger Gramunt , Santiago Galan , Toni Juan , Jesus Corbal , Federico Ardanaz , Isaac Hernandez
发明人： Roger Espasa , Joel Emer , Geoff Lowney , Roger Gramunt , Santiago Galan , Toni Juan , Jesus Corbal , Federico Ardanaz , Isaac Hernandez
IPC分类号： G06F15/16
CPC分类号： G06F12/1027 , G06F12/0844 , Y02D10/13
摘要： In one embodiment, the present invention includes an apparatus having a register file to store vector data, an address generator coupled to the register file to generate addresses for a vector memory operation, and a controller to generate an output slice from one or more slices each including multiple addresses, where the output slice includes addresses each corresponding to a separately addressable portion of a memory. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明包括具有用于存储矢量数据的寄存器文件的装置，耦合到寄存器文件以产生矢量存储器操作的地址的地址发生器，以及控制器，用于从一个或多个片段生成输出片段 包括多个地址，其中输出切片包括各自对应于存储器的单独可寻址部分的地址。 描述和要求保护其他实施例。
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公开(公告)号：US20070094477A1
公开(公告)日：2007-04-26
申请号：US11255676
申请日：2005-10-21
申请人： Roger Espasa , Joel Emer , Geoff Lowney , Roger Gramunt , Santiago Galan , Toni Juan , Jesus Corbal , Federico Ardanaz , Isaac Hernandez
发明人： Roger Espasa , Joel Emer , Geoff Lowney , Roger Gramunt , Santiago Galan , Toni Juan , Jesus Corbal , Federico Ardanaz , Isaac Hernandez
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F12/0844 , Y02D10/13
摘要： In one embodiment, the present invention includes an apparatus having a register file to store vector data, an address generator coupled to the register file to generate addresses for a vector memory operation, and a controller to generate an output slice from one or more slices each including multiple addresses, where the output slice includes addresses each corresponding to a separately addressable portion of a memory. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明包括具有用于存储矢量数据的寄存器文件的装置，耦合到寄存器文件以产生矢量存储器操作的地址的地址发生器，以及控制器，用于从一个或多个片段生成输出片段 包括多个地址，其中输出切片包括各自对应于存储器的单独可寻址部分的地址。 描述和要求保护其他实施例。
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