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公开(公告)号：US20140052969A1
公开(公告)日：2014-02-20
申请号：US13976997
申请日：2011-12-23
IPC分类号： G06F9/30
CPC分类号： G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30036 , G06F9/30145 , G06F9/3893
摘要： A processing core is described having execution unit logic circuitry having a first register to store a first vector input operand, a second register to a store a second vector input operand and a third register to store a packed data structure containing scalar input operands a, b, c. The execution unit logic circuitry further include a multiplier to perform the operation (a*(first vector input operand))+(b*(second vector operand))+c.
摘要翻译： 描述处理核心，其具有执行单元逻辑电路，其具有第一寄存器以存储第一向量输入操作数，第二寄存器存储第二向量输入操作数和第三寄存器以存储包含标量输入操作数a，b的打包数据结构 ， C。 执行单元逻辑电路还包括执行操作的乘法器（a *（第一向量输入操作数））+（b *（第二向量操作数））+ c。
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公开(公告)号：US09792115B2
公开(公告)日：2017-10-17
申请号：US13976997
申请日：2011-12-23
CPC分类号： G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30036 , G06F9/30145 , G06F9/3893
摘要： A processing core is described having execution unit logic circuitry having a first register to store a first vector input operand, a second register to a store a second vector input operand and a third register to store a packed data structure containing scalar input operands a, b, c. The execution unit logic circuitry further include a multiplier to perform the operation (a*(first vector input operand))+(b*(second vector operand))+c.
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公开(公告)号：US09766886B2
公开(公告)日：2017-09-19
申请号：US13977736
申请日：2011-12-16
IPC分类号： G06F9/302 , G06F9/315 , G06F17/17 , G09G5/00 , G06F15/76 , G06F9/30 , G06F9/38 , G06T3/40 , G06F15/80
CPC分类号： G06F9/30036 , G06F9/30007 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30032 , G06F9/30109 , G06F9/30145 , G06F9/3016 , G06F9/30185 , G06F9/3836 , G06F15/8053 , G06F17/17 , G06T3/4007
摘要： Instructions and logic provide vector linear interpolation functionality. In some embodiments, responsive to an instruction specifying: a first operand from a set of vector registers, a size of each of the vector elements, a portion of the vector elements upon which to compute linear interpolations, a second operand from a set of vector registers, and a third operand; an execution unit, reads a first, a second and a third value of the size of vector elements from corresponding data fields in the first, the second and the third operand respectively and computes an interpolated value as the first value multiplied by the second value minus the second value multiplied by the third value plus the third value.
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公开(公告)号：US20140052968A1
公开(公告)日：2014-02-20
申请号：US13976404
申请日：2011-12-23
IPC分类号： G06F9/30
CPC分类号： G06F9/3001 , G06F9/30018 , G06F9/30036 , G06F9/30101 , G06F9/30145
摘要： A method of processing an instruction is described that includes fetching and decoding the instruction. The instruction has separate destination address, first operand source address and second operand source address components. The first operand source address identifies a location of a first mask pattern in mask register space. The second operand source address identifies a location of a second mask pattern in the mask register space. The method further includes fetching the first mask pattern from the mask register space; fetching the second mask pattern from the mask register space; merging the first and second mask patterns into a merged mask pattern; and, storing the merged mask pattern at a storage location identified by the destination address.
摘要翻译： 描述了处理指令的方法，其包括获取和解码指令。 该指令具有单独的目标地址，第一个操作数源地址和第二个操作数源地址组件。 第一个操作数源地址标识掩码寄存器空间中第一个掩码模式的位置。 第二操作数源地址在掩码寄存器空间中标识第二掩码图案的位置。 该方法还包括从掩模寄存器空间获取第一掩模图案; 从掩模寄存器空间中取出第二掩模图案; 将第一和第二掩模图案合并成合并的掩模图案; 以及将合并的掩模图案存储在由目的地地址识别的存储位置。
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公开(公告)号：US09733935B2
公开(公告)日：2017-08-15
申请号：US13976404
申请日：2011-12-23
IPC分类号： G06F9/30
CPC分类号： G06F9/3001 , G06F9/30018 , G06F9/30036 , G06F9/30101 , G06F9/30145
摘要： A method of processing an instruction is described that includes fetching and decoding the instruction. The instruction has separate destination address, first operand source address and second operand source address components. The first operand source address identifies a location of a first mask pattern in mask register space. The second operand source address identifies a location of a second mask pattern in the mask register space. The method further includes fetching the first mask pattern from the mask register space; fetching the second mask pattern from the mask register space; merging the first and second mask patterns into a merged mask pattern; and, storing the merged mask pattern at a storage location identified by the destination address.
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公开(公告)号：US09465580B2
公开(公告)日：2016-10-11
申请号：US13991892
申请日：2011-12-21
CPC分类号： G06F7/57 , G06F1/02 , G06F1/03 , G06F1/0356 , G06F7/544 , G06F7/552 , G06F9/30014 , G06F9/3832 , G06F2101/08 , G06F2101/10 , G06F2101/12 , G06F2207/5521
摘要： A math circuit for computing an estimate of a transcendental function is described. A lookup table storage circuit has stored therein several groups of binary values, where each group of values represents a respective coefficient of a first polynomial that estimates the function to a high precision. A computing circuit uses a portion of a binary value, that is also taken from one of the groups of values, to evaluate a second polynomial that estimates the function to a low precision. Other embodiments are also described and claimed.
摘要翻译： 描述了一种用于计算超验函数估计的数学电路。 查找表存储电路中存储有几组二进制值，其中每组值表示将功能估计为高精度的第一多项式的相应系数。 计算电路使用二进制值的一部分，其也取自值组中的一组，以评估将功能估计为低精度的第二多项式。 还描述和要求保护其他实施例。
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7.发明授权Clock distribution system for selectively enabling clock signals to portions of a pipelined circuit 失效时钟分配系统，用于选择性地将时钟信号发送到流水线电路的部分公开(公告)号：US06611920B1
公开(公告)日：2003-08-26
申请号：US09489153
申请日：2000-01-21
IPC分类号： G06F132
CPC分类号： G06F1/3237 , G06F1/04 , G06F1/32 , Y02D10/128
摘要： A hierarchical power control system for an integrated circuit may be integrated into a clocking system that includes a global clock generator, a clock distribution network in communication with the global clock generator and a plurality of functional unit blocks each in communication with the global clock generator. The hierarchical power control system may include a first power controller provided in a communication path between the global clock generator and the clock distribution network, and a plurality of second power controllers, one provided in each communication path between the clock distribution network and a functional unit block.
摘要翻译： 用于集成电路的分级功率控制系统可以被集成到时钟系统中，该时钟系统包括全局时钟发生器，与全局时钟发生器通信的时钟分配网络和与全局时钟发生器通信的多个功能单元模块。 分级功率控制系统可以包括设置在全球时钟发生器和时钟分配网络之间的通信路径中的第一功率控制器和多个第二功率控制器，一个设置在时钟分配网络和功能单元之间的每个通信路径中 块。
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8.发明授权Processor having execution core sections operating at different clock rates 失效具有执行核心部分以不同时钟速率工作的处理器公开(公告)号：US06216234B1
公开(公告)日：2001-04-10
申请号：US09092353
申请日：1998-06-05
IPC分类号： G06F104
CPC分类号： G06F9/3842 , G06F1/08 , G06F9/30145 , G06F9/383 , G06F9/3836 , G06F9/384 , G06F9/3863 , G06F9/3869 , G06F15/7832
摘要： A processor including a first execution core section clocked to perform execution operations at a first clock frequency, and a second execution core section clocked to perform execution operations at a second clock frequency which is different than the first clock frequency. The second execution core section runs faster and includes a data cache and critical ALU functions, while the first execution core section includes latency-tolerant functions such as instruction fetch and decode units and non-critical ALU functions. The processor may further include an I/O ring which may be still slower than the first execution core section. Optionally, the first execution core section may include a third execution core section whose clock rate is between that of the first and second execution core sections. Clock multipliers/dividers may be used between the various sections to derive their clocks from a single source, such as the I/O clock.
摘要翻译： 一种处理器，包括以第一时钟频率执行执行操作的第一执行核心部分和第二执行核心部分，其被计时以在与第一时钟频率不同的第二时钟频率执行执行操作。 第二个执行核心部分运行速度更快，包括数据高速缓存和关键的ALU功能，而第一个执行核心部分包括延迟容忍功能，如指令提取和解码单元以及非关键ALU功能。 处理器还可以包括可能仍然比第一执行核心部分慢的I / O环。 可选地，第一执行核心部分可以包括其时钟速率在第一执行核心部分和第二执行核心部分之间的第三执行核心部分。 可以在各部分之间使用时钟乘法器/分频器，以从单个源（例如I / O时钟）导出其时钟。
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9.发明授权
公开(公告)号：US5942917A
公开(公告)日：1999-08-24
申请号：US999102
申请日：1997-12-29
IPC分类号： H03K19/20 , H03K19/0948 , H03K19/096 , H03K19/094
CPC分类号： H03K19/0963 , H03K19/0948
摘要： A logic structure adapted to receive pulsed active input signals produces a logical output with a very small inherent switching delay. Pull-down transistors and complementary pull-up transistors are ratioed such that the default logical output level remains close to nominal even when the logic structure sinks or sources a DC current. When the pulsed input signals are inactive, no DC current path is enabled.
摘要翻译： 适于接收脉冲有源输入信号的逻辑结构产生具有非常小的固有切换延迟的逻辑输出。 比较下拉晶体管和互补上拉晶体管，使得默认逻辑输出电平保持接近标称值，即使当逻辑结构吸收或输出直流电流时。 当脉冲输入信号无效时，不启用直流电流路径。
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公开(公告)号：US5899974A
公开(公告)日：1999-05-04
申请号：US775786
申请日：1996-12-31
CPC分类号： G10L19/0018
摘要： A method for compressing speech. An audio signal comprising speech is broken down into its phonetic components. These phonetic components are then converted into data elements that represent each of the phonetic components. The determination of data elements is accomplished using a predefined table that correlates phonetic sounds to data elements. The data elements representing the phonetic sounds are then stored.
摘要翻译： 压缩语音的方法。 包括语音的音频信号被分解成其语音分量。 然后，这些语音分量被转换成表示每个语音分量的数据元素。 使用将语音与数据元素相关联的预定义表来完成数据元素的确定。 然后存储表示语音的数据元素。
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