公开(公告)号：US20160064425A1

公开(公告)日：2016-03-03

申请号：US14721505

申请日：2015-05-26

Applicant: Samsung Display Co., Ltd.

Inventor： Myounghwa KIM ,  Jaewook Kang ,  Joohee Jeon ,  Jongchan Lee ,  Yoonho Khang

IPC: H01L27/12 ,  H01L29/49 ,  G02F1/1362 ,  H01L29/786 ,  H01L27/32 ,  G02F1/1368 ,  H01L29/423 ,  H01L29/45

CPC classification number: H01L27/1255 ,  G02F1/136213 ,  G02F1/1368 ,  H01L27/1222 ,  H01L27/1288 ,  H01L27/3258 ,  H01L27/3262 ,  H01L27/3265 ,  H01L29/42372 ,  H01L29/42384 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/78666 ,  H01L29/78675 ,  H01L2227/323

Abstract: Provided is a thin film transistor array substrate having at least one thin film transistor. The thin film transistor includes a semiconductor layer having a channel area with a first doping concentration on a substrate, a source-drain area disposed at opposite sides of the channel area and with a second doping concentration greater than the first doping concentration, and a substantially undoped area extending from the source-drain area. The substrate has a gate insulating layer on the semiconductor layer and a gate electrode disposed on the gate insulating layer and overlapping the channel area in at least some portions. The substrate has a source electrode and a drain electrode, each insulated from the gate electrode and electrically connected to the source-drain area. The gate electrode includes a first gate electrode layer and a second gate electrode layer, wherein the second gate electrode layer is thicker than the first gate electrode layer.

Abstract translation: 提供了具有至少一个薄膜晶体管的薄膜晶体管阵列基板。 薄膜晶体管包括半导体层，其具有在衬底上具有第一掺杂浓度的沟道区，设置在沟道区的相对侧并具有大于第一掺杂浓度的第二掺杂浓度的源极 - 漏极区，以及基本上 从源极 - 漏极区域延伸的未掺杂区域。 衬底在半导体层上具有栅极绝缘层，栅极电极设置在栅极绝缘层上并且至少部分地与沟道区域重叠。 基板具有源电极和漏电极，各自与栅电极绝缘并且电连接到源漏区。 栅电极包括第一栅电极层和第二栅极电极层，其中第二栅电极层比第一栅电极层厚。