公开(公告)号：US09842794B2

公开(公告)日：2017-12-12

申请号：US14945291

申请日：2015-11-18

申请人： STMICROELECTRONICS, INC.

发明人： Ela Mia Cadag ,  Jefferson Talledo

IPC分类号： H01L23/495 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00

CPC分类号： H01L23/4952 ,  H01L21/4828 ,  H01L21/56 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/4951 ,  H01L23/49548 ,  H01L23/49568 ,  H01L23/49582 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/81 ,  H01L24/83 ,  H01L24/97 ,  H01L2224/16245 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81002 ,  H01L2224/81986 ,  H01L2224/83002 ,  H01L2224/83101 ,  H01L2224/83385 ,  H01L2224/83986 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2224/13099 ,  H01L2924/00

摘要： One or more embodiments are directed to semiconductor packages having an integrated heatsink and methods of forming same. In one embodiment, a package includes a plurality of leads that support and enclose periphery portions of the semiconductor die. The leads have first and second, opposing surfaces that form outer surfaces of the package. The first surface of the leads may form a heatsink and the second surface of the leads form lands of the package for coupling to another device, substrate, or board. The package includes encapsulation material that surrounds the semiconductor die and located between upper portions of the leads. The package further includes a back filling material (or insulating material) that is below the semiconductor die and between lower portions of the leads.

公开(公告)号：US09536756B1

公开(公告)日：2017-01-03

申请号：US14754143

申请日：2015-06-29

申请人： STMicroelectronics, Inc.

发明人： Jefferson Talledo ,  Amor Zapanta

IPC分类号： H01L21/00 ,  H01L21/56 ,  H01L21/48 ,  H01L21/78

CPC分类号： H01L21/566 ,  H01L21/4825 ,  H01L21/4832 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3107 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/181 ,  H01L2924/00012

摘要： One or more embodiments are directed to semiconductor packages that are assembled using a sacrificial material, that when removed, separates the assembled packages into individual packages. The sacrificial material may be removed by a blanket technique such that a mask, pattern, or alignment step is not needed. In one embodiment the sacrificial material is formed on the lead frame on a connecting bar of a lead frame between adjacent leads. After the molding step, the connecting bar is etched away exposing a surface of the sacrificial material. The sacrificial material is removed, thereby separating the assembled packages into individual packages.

摘要翻译： 一个或多个实施例涉及使用牺牲材料组装的半导体封装，当被移除时，将组装的封装分离成单个封装。 可以通过覆盖技术去除牺牲材料，使得不需要掩模，图案或对准步骤。 在一个实施例中，牺牲材料形成在引线框架上的相邻引线之间的引线框架的连接杆上。 在模制步骤之后，连接杆被蚀刻掉，暴露牺牲材料的表面。 去除牺牲材料，从而将组装的包装分离成单独的包装。

公开(公告)号：US20160379846A1

公开(公告)日：2016-12-29

申请号：US14754143

申请日：2015-06-29

申请人： STMicroelectronics, Inc.

发明人： Jefferson Talledo ,  Amor Zapanta

IPC分类号： H01L21/56 ,  H01L21/78 ,  H01L21/48

CPC分类号： H01L21/566 ,  H01L21/4825 ,  H01L21/4832 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3107 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/181 ,  H01L2924/00012

摘要： One or more embodiments are directed to semiconductor packages that are assembled using a sacrificial material, that when removed, separates the assembled packages into individual packages. The sacrificial material may be removed by a blanket technique such that a mask, pattern, or alignment step is not needed. In one embodiment the sacrificial material is formed on the lead frame on a connecting bar of a lead frame between adjacent leads. After the molding step, the connecting bar is etched away exposing a surface of the sacrificial material. The sacrificial material is removed, thereby separating the assembled packages into individual packages.

摘要翻译： 一个或多个实施例涉及使用牺牲材料组装的半导体封装，当被移除时，将组装的封装分离成单个封装。 可以通过覆盖技术去除牺牲材料，使得不需要掩模，图案或对准步骤。 在一个实施例中，牺牲材料形成在引线框架上的相邻引线之间的引线框架的连接杆上。 在模制步骤之后，连接杆被蚀刻掉，暴露牺牲材料的表面。 去除牺牲材料，从而将组装的包装分离成单独的包装。