公开(公告)号：US20100165742A1

公开(公告)日：2010-07-01

申请号：US12721913

申请日：2010-03-11

申请人： Dong-Hyuk Chae ,  Young-Ho Lim

发明人： Dong-Hyuk Chae ,  Young-Ho Lim

IPC分类号： G11C16/04 ,  G05F1/10

CPC分类号： G11C16/12 ,  G11C5/145 ,  G11C16/0483

摘要： Methods of generating a program voltage for programming a non-volatile memory device include generating an initial voltage and generating a first ramping voltage in response to the initial voltage. The first ramping voltage has a ramping speed slower than the ramping speed of the initial voltage. A second ramping voltage is generated in response to the first ramping voltage. The second ramping voltage has a lower ripple than the first ramping voltage. The second ramping voltage is output as a program voltage for programming a non-volatile memory device. A program voltage generating circuit includes a program voltage generating unit configured to generate an initial voltage, a ramping circuit configured to generate a first ramping voltage responsive to the initial voltage, and a voltage controlling unit configured to generate a second ramping voltage having relatively low ripple and to output the first ramping voltage or the second ramping voltage responsive to a voltage level of the first ramping voltage. Semiconductor memory devices including program voltage generating circuits are also disclosed.

摘要翻译： 产生用于编程非易失性存储器件的编程电压的方法包括产生初始电压并响应于初始电压产生第一斜变电压。 第一斜坡电压的斜坡速度比初始电压的斜坡速度慢。 响应于第一斜坡电压产生第二斜坡电压。 第二斜坡电压具有比第一斜坡电压更低的纹波。 输出第二斜坡电压作为编程非易失性存储器件的编程电压。 一个编程电压发生电路包括：一个编程电压产生单元，被配置为产生一个初始电压;一个斜坡电路，被配置为产生一个响应初始电压的第一斜坡电压;以及一个电压控制单元，被配置为产生一个具有相对低纹波的第二斜坡电压 并且响应于第一斜坡电压的电压电平而输出第一斜坡电压或第二斜坡电压。 还公开了包括程序电压产生电路的半导体存储器件。

公开(公告)号：US07701772B2

公开(公告)日：2010-04-20

申请号：US12186087

申请日：2008-08-05

申请人： Dong-Hyuk Chae ,  Young-Ho Lim

发明人： Dong-Hyuk Chae ,  Young-Ho Lim

IPC分类号： G11C16/04

CPC分类号： G11C16/12 ,  G11C5/145 ,  G11C16/0483

摘要： Methods of generating a program voltage for programming a non-volatile memory device include generating an initial voltage and generating a first ramping voltage in response to the initial voltage. The first ramping voltage has a ramping speed slower than the ramping speed of the initial voltage. A second ramping voltage is generated in response to the first ramping voltage. The second ramping voltage has a lower ripple than the first ramping voltage. The second ramping voltage is output as a program voltage for programming a non-volatile memory device. A program voltage generating circuit includes a program voltage generating unit configured to generate an initial voltage, a ramping circuit configured to generate a first ramping voltage responsive to the initial voltage, and a voltage controlling unit configured to generate a second ramping voltage having relatively low ripple and to output the first ramping voltage or the second ramping voltage responsive to a voltage level of the first ramping voltage. Semiconductor memory devices including program voltage generating circuits are also disclosed.

摘要翻译： 产生用于编程非易失性存储器件的编程电压的方法包括产生初始电压并响应于初始电压产生第一斜变电压。 第一斜坡电压的斜坡速度比初始电压的斜坡速度慢。 响应于第一斜坡电压产生第二斜坡电压。 第二斜坡电压具有比第一斜坡电压更低的纹波。 输出第二斜坡电压作为编程非易失性存储器件的编程电压。 一个编程电压发生电路包括：一个编程电压产生单元，被配置为产生一个初始电压;一个斜坡电路，被配置为产生一个响应初始电压的第一斜坡电压;以及一个电压控制单元，被配置为产生一个具有相对低纹波的第二斜坡电压 并且响应于第一斜坡电压的电压电平而输出第一斜坡电压或第二斜坡电压。 还公开了包括程序电压产生电路的半导体存储器件。

公开(公告)号：US07697327B2

公开(公告)日：2010-04-13

申请号：US12145531

申请日：2008-06-25

申请人： Moo-Sung Kim ,  Young-Ho Lim

发明人： Moo-Sung Kim ,  Young-Ho Lim

IPC分类号： G11C16/00

CPC分类号： G11C16/12 ,  G11C8/08 ,  G11C16/0483

摘要： A NAND flash memory device and a programming method thereof capable of improving a program speed during a multi-level cell programming operation are provided. The device performs a programming operation using an ISPP method. Additionally, the device includes a memory cell storing multi-bit data; a program voltage generating circuit generating a program voltage to be supplied to the memory cell; and a program voltage controller controlling a start level of the program voltage. The device supplies an LSB start voltage to a selected word line during an LSB program, and an MSB start voltage higher than the LSB start voltage to the selected word line during an MSB program.

摘要翻译： 提供一种能够在多级单元编程操作期间提高编程速度的NAND快闪存储器件及其编程方法。 该设备使用ISPP方法执行编程操作。 另外，该设备包括存储多位数据的存储单元; 编程电压产生电路，产生要提供给存储单元的编程电压; 以及控制编程电压的起始电平的编程电压控制器。 在MSB程序期间，器件在LSB程序期间将LSB起始电压提供给所选择的字线，并在MSB程序期间向所选字线提供高于LSB起始电压的MSB启动电压。

公开(公告)号：US07675774B2

公开(公告)日：2010-03-09

申请号：US12333344

申请日：2008-12-12

申请人： Sung-Soo Lee ,  Young-Ho Lim ,  Hyun-Chul Cho ,  Dong-Hyuk Chae

发明人： Sung-Soo Lee ,  Young-Ho Lim ,  Hyun-Chul Cho ,  Dong-Hyuk Chae

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C2211/5642

摘要： According to one aspect, a memory cell array includes a bit line connected to a plurality of nonvolatile memory cells, where the nonvolatile memory cells are selectively programmable in any one of at least first, second, third and fourth threshold voltage states, and where the first, second, third and fourth threshold voltage states correspond to four different data values defined by first and second bits. A page buffer circuit stores a logic value as main latch data and is responsive to a main latch signal to selectively flip the logic value of the main latch data according to a voltage level of the bit line. A sub-latch circuit stores a logic value as sub-latch data and is responsive to a sub-latch signal to selectively flip the logic value of the sub-latch data according to the voltage level of the bit line. The memory device is operable in a read mode which reads the threshold voltage state of the non-volatile memory cells and a programming mode which programs the threshold voltage state of the non-volatile memory cells, wherein the page buffer circuit is selectively responsive to the sub-latch data to inhibit flipping of the logic value of the main latch data in the programming mode.

摘要翻译： 根据一个方面，存储单元阵列包括连接到多个非易失性存储单元的位线，其中非易失性存储单元可选择性地以至少第一，第二，第三和第四阈值电压状态中的任何一个编程，并且其中 第一，第二，第三和第四阈值电压状态对应于由第一和第二位定义的四个不同的数据值。 页面缓冲电路将逻辑值存储为主锁存数据，并且响应于主锁存信号，以根据位线的电压电平选择性地翻转主锁存数据的逻辑值。 子锁存电路将逻辑值存储为子锁存数据，并且响应于子锁存信号，以根据位线的电压电平选择性地翻转子锁存数据的逻辑值。 存储器件可读取读取非易失性存储器单元的阈值电压状态的读取模式和编程非易失性存储器单元的阈值电压状态的编程模式，其中页面缓冲器电路有选择地响应于 子锁存数据，以禁止在编程模式下翻转主锁存器数据的逻辑值。

公开(公告)号：US07619929B2

公开(公告)日：2009-11-17

申请号：US12201977

申请日：2008-08-29

申请人： Dong-Hyuk Chae ,  Young-Ho Lim

发明人： Dong-Hyuk Chae ,  Young-Ho Lim

IPC分类号： G11C11/34

CPC分类号： G11C8/08 ,  G11C16/349

摘要： A non-volatile semiconductor memory device includes: cell strings connected to respective bit lines; each of the cell strings having a string select transistor connected to a string select line, a ground select transistor connected to a ground select line, and memory cells connected to corresponding word lines and connected in series between the string select transistor and the ground select transistor; a first voltage drop circuit configured to reduce an applied read voltage during a read operation; a second voltage drop circuit configured to reduce the applied read voltage; a string select line driver circuit configured to drive the string select line with the reduced voltage provided by the first voltage drop circuit; and a ground select line driver circuit configured to drive a ground select line with the reduced voltage provided by the second voltage drop circuit.

摘要翻译： 非易失性半导体存储器件包括：连接到相应位线的单元串; 每个单元串具有连接到串选择线的串选择晶体管，连接到接地选择线的接地选择晶体管和连接到对应字线并且串联连接在串选择晶体管和接地选择晶体管之间的存储单元 ; 第一电压降电路，被配置为在读取操作期间减小施加的读取电压; 配置为减小所施加的读取电压的第二电压降电路; 串行选择线驱动电路，被配置为利用由第一压降电路提供的降低的电压驱动串选择线; 以及接地选择线驱动电路，被配置为用由第二压降电路提供的降低的电压来驱动接地选择线。

公开(公告)号：US07468907B2

公开(公告)日：2008-12-23

申请号：US11522406

申请日：2006-09-18

申请人： Dong-Ku Kang ,  Young-Ho Lim

发明人： Dong-Ku Kang ,  Young-Ho Lim

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/12 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621

摘要： A program method of a flash memory device including a plurality of memory cells for storing multi-bit data indicating one of states. The program method includes programming memory cells selected to have one of the states by using multi-bit data; detecting programmed memory cells within a predetermined region of a threshold voltage distribution where the programmed memory cells having the respective states are distributed, wherein the predetermined region of the respective states is selected by one of a first verify voltage and a read voltage and a second voltage, the first verify voltage being lower than the second verify voltage and higher than the read voltage; and programming the detected memory cells to have a threshold voltage being equivalent to or higher than the second verify voltage corresponding to each of the states.

摘要翻译： 一种闪存器件的编程方法，包括用于存储指示状态之一的多位数据的多个存储器单元。 程序方法包括通过使用多位数据来编程选择为具有状态之一的存储器单元; 在阈值电压分布的预定区域内检测已编程的存储单元，其中具有各自状态的编程存储单元被分配，其中各个状态的预定区域由第一验证电压和读取电压和第二电压 第一验证电压低于第二验证电压并高于读取电压; 以及对检测到的存储单元进行编程，使阈值电压等于或高于对应于每个状态的第二验证电压。

公开(公告)号：US07463526B2

公开(公告)日：2008-12-09

申请号：US11513159

申请日：2006-08-31

申请人： Dong-Ku Kang ,  Young-Ho Lim

发明人： Dong-Ku Kang ,  Young-Ho Lim

IPC分类号： G11C11/34

CPC分类号： G11C16/12 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C2211/5621

摘要： A programming method of a flash memory device having a plurality of memory cells for storing multi-bit data indicating one of a plurality of states. The programming method includes programming selected memory cells using multi-bit data to have one of the states; detecting programmed memory cells arranged within a predetermined region of threshold voltage distribution each corresponding to at least two of the states, wherein predetermined regions of the respective at least two states are selected by one of a first verify voltage and a read voltage and a second verify voltage, the first verify voltage being lower than the second verify voltage and higher than the read voltage; and simultaneously programming detected memory cells of the at least two states to have a threshold voltage being equivalent to or higher than the second verify voltage corresponding to each of the states.

摘要翻译： 一种具有多个存储单元的闪速存储器件的编程方法，用于存储指示多个状态之一的多位数据。 编程方法包括使用多位数据对所选择的存储单元进行编程以具有其中一种状态; 检测布置在每个对应于至少两个状态的阈值电压分布的预定区域内的程序存储器单元，其中相应的至少两个状态的预定区域由第一验证电压和读取电压中的一个选择，并且第二验证 电压，第一验证电压低于第二验证电压并高于读取电压; 同时对所述至少两个状态的检测到的存储单元进行编程，以使阈值电压等于或高于对应于每个状态的第二验证电压。

公开(公告)号：US07433235B2

公开(公告)日：2008-10-07

申请号：US11320096

申请日：2005-12-28

申请人： Dong-Hyuk Chae ,  Young-Ho Lim

发明人： Dong-Hyuk Chae ,  Young-Ho Lim

IPC分类号： G11C11/34

CPC分类号： G11C8/08 ,  G11C16/349

摘要： A non-volatile semiconductor memory device includes: cell strings connected to respective bit lines; each of the cell strings having a string select transistor connected to a string select line, a ground select transistor connected to a ground select line, and memory cells connected to corresponding word lines and connected in series between the string select transistor and the ground select transistor; a first voltage drop circuit configured to reduce an applied read voltage during a read operation; a second voltage drop circuit configured to reduce the applied read voltage; a string select line driver circuit configured to drive the string select line with the reduced voltage provided by the first voltage drop circuit; and a ground select line driver circuit configured to drive a ground select line with the reduced voltage provided by the second voltage drop circuit.

摘要翻译： 非易失性半导体存储器件包括：连接到相应位线的单元串; 每个单元串具有连接到串选择线的串选择晶体管，连接到接地选择线的接地选择晶体管和连接到对应字线并且串联连接在串选择晶体管和接地选择晶体管之间的存储单元 ; 第一电压降电路，被配置为在读取操作期间减小施加的读取电压; 配置为减小所施加的读取电压的第二电压降电路; 串行选择线驱动电路，被配置为利用由第一压降电路提供的降低的电压驱动串选择线; 以及接地选择线驱动电路，被配置为用由第二压降电路提供的降低的电压来驱动接地选择线。

公开(公告)号：US07420856B2

公开(公告)日：2008-09-02

申请号：US11294810

申请日：2005-12-06

申请人： Dong-Hyuk Chae ,  Young-Ho Lim

发明人： Dong-Hyuk Chae ,  Young-Ho Lim

IPC分类号： G11C5/14

CPC分类号： G11C16/12 ,  G11C5/145 ,  G11C16/0483

摘要： Methods of generating a program voltage for programming a non-volatile memory device include generating an initial voltage and generating a first ramping voltage in response to the initial voltage. The first ramping voltage has a ramping speed slower than the ramping speed of the initial voltage. A second ramping voltage is generated in response to the first ramping voltage. The second ramping voltage has a lower ripple than the first ramping voltage. The second ramping voltage is output as a program voltage for programming a non-volatile memory device. A program voltage generating circuit includes a program voltage generating unit configured to generate an initial voltage, a ramping circuit configured to generate a first ramping voltage responsive to the initial voltage, and a voltage controlling unit configured to generate a second ramping voltage having relatively low ripple and to output the first ramping voltage or the second ramping voltage responsive to a voltage level of the first ramping voltage. Semiconductor memory devices including program voltage generating circuits are also disclosed.

摘要翻译： 产生用于编程非易失性存储器件的编程电压的方法包括产生初始电压并响应于初始电压产生第一斜变电压。 第一斜坡电压的斜坡速度比初始电压的斜坡速度慢。 响应于第一斜坡电压产生第二斜坡电压。 第二斜坡电压具有比第一斜坡电压更低的纹波。 输出第二斜坡电压作为编程非易失性存储器件的编程电压。 一个编程电压发生电路包括：一个编程电压产生单元，被配置为产生一个初始电压;一个斜坡电路，被配置为产生一个响应初始电压的第一斜坡电压;以及一个电压控制单元，被配置为产生一个具有相对低纹波的第二斜坡电压 并且响应于第一斜坡电压的电压电平而输出第一斜坡电压或第二斜坡电压。 还公开了包括程序电压产生电路的半导体存储器件。

公开(公告)号：US07403429B2

公开(公告)日：2008-07-22

申请号：US11548630

申请日：2006-10-11

申请人： Dong-Hyuk Chae ,  Young-Ho Lim

发明人： Dong-Hyuk Chae ,  Young-Ho Lim

IPC分类号： G11C11/34

CPC分类号： G11C16/16 ,  G11C16/08

摘要： A method of erasing data in a nonvolatile semiconductor memory device including applying an erase voltage to a substrate of the semiconductor memory device, applying a ground voltage to wordlines of a selected memory cell string formed in the substrate, and applying a control voltage to at least one of a string selection line and a ground selection line of the selected memory cell string.

摘要翻译： 一种擦除非易失性半导体存储器件中的数据的方法，包括向半导体存储器件的衬底施加擦除电压，将接地电压施加到形成在衬底中的所选择的存储器单元串的字线，并将控制电压施加至少 选择的存储单元串的字符串选择行和地选择行之一。