公开(公告)号：US20230387036A1

公开(公告)日：2023-11-30

申请号：US17826764

申请日：2022-05-27

Applicant: Texas Instruments Incorporated

Inventor： Michael Todd Wyant ,  Joseph O. Liu ,  Christopher Daniel Manack

IPC: H01L23/544 ,  H01L23/31 ,  H01L23/495 ,  H01L23/00 ,  H01L21/66 ,  H01L21/56 ,  H01L21/268

CPC classification number: H01L23/544 ,  H01L23/3107 ,  H01L23/495 ,  H01L24/48 ,  H01L22/12 ,  H01L21/56 ,  H01L21/268 ,  H01L2224/48245 ,  H01L2223/5446

Abstract: A method includes performing a laser ablation process that removes a portion of a wafer to form a trench in a scribe region between adjacent die regions of the wafer, the trench extending from a first side of the wafer toward an opposite second side of the wafer, the trench extending through a metallization structure and an active circuit portion of the wafer, and a bottom of the trench spaced apart from the second side of the wafer. The method also includes performing a wafer expansion process that separates individual semiconductor dies from the wafer after the laser ablation process.

公开(公告)号：US11664276B2

公开(公告)日：2023-05-30

申请号：US16205692

申请日：2018-11-30

Applicant: Texas Instruments Incorporated

Inventor： Matthew John Sherbin ,  Michael Todd Wyant ,  Christopher Daniel Manack ,  Hiroyuki Sada ,  Shoichi Iriguchi ,  Genki Yano ,  Ming Zhu ,  Joseph O. Liu

IPC: H01L23/544 ,  H01L21/78 ,  B23K26/364 ,  H01L23/00 ,  H01L21/268

CPC classification number: H01L21/78 ,  B23K26/364 ,  H01L21/268 ,  H01L23/562

Abstract: A semiconductor die includes a substrate having a semiconductor surface layer bon a front side with active circuitry including at last one transistor therein and a back side. The sidewall edges of the semiconductor die have at least one damage region pair including an angled damage feature region relative to a surface normal of the semiconductor die that is above a damage region that is more normal to the surface normal of the die as compared to the angled damage feature region.

公开(公告)号：US11616038B2

公开(公告)日：2023-03-28

申请号：US17094723

申请日：2020-11-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Patrick Francis Thompson ,  Christopher Daniel Manack ,  Stefan Herzer ,  Rakshit Agrawal

IPC: H01L23/495 ,  H01L23/00

Abstract: A semiconductor die includes a substrate and an integrated circuit provided on the substrate and having contacts. An electrically conductive layer is provided on the integrated circuit and defines electrically conductive elements electrically connected to the contacts. Electrically conductive interconnects coupled with respective electrically conductive elements. The electrically conductive interconnects have at least one of different sizes or shapes from one another.

公开(公告)号：US20230005807A1

公开(公告)日：2023-01-05

申请号：US17931828

申请日：2022-09-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Nazila Dadvand ,  Keith Edward Johnson ,  Christopher Daniel Manack ,  Salvatore Frank Pavone

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L23/538 ,  H01L23/498 ,  H01L25/065

Abstract: A device includes a semiconductor die including a via, a layer of titanium tungsten (TiW) in contact with the via, and a copper pillar including a top portion and a bottom portion. The bottom portion is in contact with the layer of TiW. The copper pillar includes interdiffused zinc within the bottom portion.

公开(公告)号：US20220406673A1

公开(公告)日：2022-12-22

申请号：US17353805

申请日：2021-06-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Vivek Swaminathan Sridharan ,  Christopher Daniel Manack ,  Joseph Liu

IPC: H01L23/31 ,  H01L23/00

Abstract: A semiconductor package includes a semiconductor substrate forming a cavity and a redistribution layer on a first side of the semiconductor substrate, the redistribution layer forming die contacts within the cavity and a set of terminals for the semiconductor package opposite the semiconductor substrate. The redistribution layer electrically connects one or more of the die contacts to the set of terminals. The semiconductor package further includes a semiconductor die including die terminals within the cavity with the die terminals electrically coupled to the die contacts within the cavity.

公开(公告)号：US20220384375A1

公开(公告)日：2022-12-01

申请号：US17884284

申请日：2022-08-09

Applicant: Texas Instruments Incorporated

Inventor： Vivek Swaminathan Sridharan ,  Christopher Daniel Manack ,  Nazila Dadvand ,  Salvatore Frank Pavone ,  Patrick Francis Thompson

IPC: H01L23/00

Abstract: In some examples, a package comprises a die and a redistribution layer coupled to the die. The redistribution layer comprises a metal layer, a brass layer abutting the metal layer, and a polymer layer abutting the brass layer.

公开(公告)号：US20220285293A1

公开(公告)日：2022-09-08

申请号：US17752037

申请日：2022-05-24

Applicant: Texas Instruments Incorporated

Inventor： Vivek Swaminathan Sridharan ,  Yiqi Tang ,  Christopher Daniel Manack ,  Rajen Manicon Murugan ,  Liang Wan ,  Hiep Xuan Nguyen

IPC: H01L23/60 ,  H01L23/495 ,  H01L23/00 ,  H01L33/00 ,  H01L33/62

Abstract: A system in a package (SIP) includes carrier layer regions that have a dielectric material with a metal post therethrough, where adjacent carrier layer regions define a gap. A driver IC die is positioned in the gap having nodes connected to bond pads exposed by openings in a top side of a first passivation layer, with the bond pads facing up. A dielectric layer is on the first passivation layer and carrier layer region that includes filled through vias coupled to the bond pads and to the metal post. A light blocking layer is on sidewalls and a bottom of the substrate. A first device includes a light emitter that has first bondable features. The light blocking layer can block at least 90% of incident light. The first bondable features are flipchip mounted to a first portion of the bond pads.

公开(公告)号：US20210398882A1

公开(公告)日：2021-12-23

申请号：US16904193

申请日：2020-06-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Patrick Francis Thompson ,  Christopher Daniel Manack ,  Madison Paige Koziol

IPC: H01L23/495

Abstract: A semiconductor package includes a semiconductor die with an active surface and an inactive surface, the active surface including metal pillars providing electrical connections to functional circuitry of the semiconductor die, and a backside metal layer on the inactive surface. The backside metal layer is attached to the inactive surface. The semiconductor package further includes a plurality of leads with each of the leads including an internal leadfinger portion and an exposed portion that includes a bonding portion. Distal ends of the metal pillars are in contact with and electrically coupled to the internal leadfinger portions. The backside metal layer is exposed on an outer surface of the semiconductor package. The bonding portions and the backside metal layer approximately planar to each other.

公开(公告)号：US11121076B2

公开(公告)日：2021-09-14

申请号：US16454847

申请日：2019-06-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Nazila Dadvand ,  Christopher Daniel Manack

IPC: H01L23/522 ,  H01L23/31 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L23/00

Abstract: A die includes a semiconductor layer, an electrical contact on a first side of the semiconductor layer, a backside electrical contact layer on second side of the semiconductor layer. The die further includes a zinc layer over at least one of the electrical contact or the backside electrical contact layer of the die, and a conversion coating over the zinc layer. The conversion coating includes at least one of zirconium and vanadium. As part of an embedded die package including the die, at least a portion of the conversion coating may adjacent to an electrically insulating substrate of the embedded die package.

公开(公告)号：US20210280547A1

公开(公告)日：2021-09-09

申请号：US17323939

申请日：2021-05-18

Applicant: Texas Instruments Incorporated

Inventor： Nazila Dadvand ,  Christopher Daniel Manack ,  Salvatore Frank Pavone

IPC: H01L23/00 ,  H01L23/495 ,  B23K1/00 ,  C25D7/12

Abstract: A microelectronic device has bump bond structures on input/output (I/O) pads. The bump bond structures include copper-containing pillars, a barrier layer including cobalt and zinc on the copper-containing pillars, and tin-containing solder on the barrier layer. The barrier layer includes 0.1 weight percent to 50 weight percent cobalt and an amount of zinc equivalent to a layer of pure zinc 0.05 microns to 0.5 microns thick. A lead frame has a copper-containing member with a similar barrier layer in an area for a solder joint. Methods of forming the microelectronic device are disclosed.