公开(公告)号：US11380637B2

公开(公告)日：2022-07-05

申请号：US16950708

申请日：2020-11-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Vivek Swaminathan Sridharan ,  Christopher Daniel Manack ,  Joseph Liu

IPC: H01L23/00

Abstract: In some examples, a chip scale package (CSP) comprises a semiconductor die; a passivation layer abutting the semiconductor die; a via extending through the passivation layer; and a first metal layer abutting the via. The CSP also includes an insulation layer abutting the first metal layer, with the insulation layer having an orifice with a maximal horizontal area of less than 32400 microns2. The CSP further includes a second metal layer abutting the insulation layer and adapted to couple to a solder ball. The second metal layer abuts the first metal layer at a point of contact defined by the orifice in the insulation layer.

公开(公告)号：US20220406673A1

公开(公告)日：2022-12-22

申请号：US17353805

申请日：2021-06-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Vivek Swaminathan Sridharan ,  Christopher Daniel Manack ,  Joseph Liu

IPC: H01L23/31 ,  H01L23/00

Abstract: A semiconductor package includes a semiconductor substrate forming a cavity and a redistribution layer on a first side of the semiconductor substrate, the redistribution layer forming die contacts within the cavity and a set of terminals for the semiconductor package opposite the semiconductor substrate. The redistribution layer electrically connects one or more of the die contacts to the set of terminals. The semiconductor package further includes a semiconductor die including die terminals within the cavity with the die terminals electrically coupled to the die contacts within the cavity.

公开(公告)号：US20220384375A1

公开(公告)日：2022-12-01

申请号：US17884284

申请日：2022-08-09

Applicant: Texas Instruments Incorporated

Inventor： Vivek Swaminathan Sridharan ,  Christopher Daniel Manack ,  Nazila Dadvand ,  Salvatore Frank Pavone ,  Patrick Francis Thompson

IPC: H01L23/00

Abstract: In some examples, a package comprises a die and a redistribution layer coupled to the die. The redistribution layer comprises a metal layer, a brass layer abutting the metal layer, and a polymer layer abutting the brass layer.

公开(公告)号：US20220285293A1

公开(公告)日：2022-09-08

申请号：US17752037

申请日：2022-05-24

Applicant: Texas Instruments Incorporated

Inventor： Vivek Swaminathan Sridharan ,  Yiqi Tang ,  Christopher Daniel Manack ,  Rajen Manicon Murugan ,  Liang Wan ,  Hiep Xuan Nguyen

IPC: H01L23/60 ,  H01L23/495 ,  H01L23/00 ,  H01L33/00 ,  H01L33/62

Abstract: A system in a package (SIP) includes carrier layer regions that have a dielectric material with a metal post therethrough, where adjacent carrier layer regions define a gap. A driver IC die is positioned in the gap having nodes connected to bond pads exposed by openings in a top side of a first passivation layer, with the bond pads facing up. A dielectric layer is on the first passivation layer and carrier layer region that includes filled through vias coupled to the bond pads and to the metal post. A light blocking layer is on sidewalls and a bottom of the substrate. A first device includes a light emitter that has first bondable features. The light blocking layer can block at least 90% of incident light. The first bondable features are flipchip mounted to a first portion of the bond pads.

公开(公告)号：US12142586B2

公开(公告)日：2024-11-12

申请号：US17809854

申请日：2022-06-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Vivek Swaminathan Sridharan ,  Christopher Daniel Manack ,  Joseph Liu

IPC: H01L23/00

Abstract: In some examples, a chip scale package (CSP) comprises a semiconductor die; a passivation layer abutting the semiconductor die; a via extending through the passivation layer; and a first metal layer abutting the via. The CSP also includes an insulation layer abutting the first metal layer, with the insulation layer having an orifice with a maximal horizontal area of less than 32400 microns2. The CSP further includes a second metal layer abutting the insulation layer and adapted to couple to a solder ball. The second metal layer abuts the first metal layer at a point of contact defined by the orifice in the insulation layer.

公开(公告)号：US20210210462A1

公开(公告)日：2021-07-08

申请号：US16734836

申请日：2020-01-06

Applicant: Texas Instruments Incorporated

Inventor： Vivek Swaminathan Sridharan ,  Enis Tuncer ,  Christopher Daniel Manack ,  Patrick Francis Thompson

IPC: H01L23/00

Abstract: A semiconductor device includes a semiconductor surface having circuitry with metal interconnect layers over the semiconductor surface including a selected metal interconnect layer providing an interconnect trace having a first and second end. A top dielectric layer is on the top metal interconnect layer. A redistribution layer (RDL) is on the top dielectric layer. A corrosion interruption structure (CIS) including the interconnect trace bridges an interrupting gap in a trace of the RDL.

公开(公告)号：US11984418B2

公开(公告)日：2024-05-14

申请号：US17884284

申请日：2022-08-09

Applicant: Texas Instruments Incorporated

Inventor： Vivek Swaminathan Sridharan ,  Christopher Daniel Manack ,  Nazila Dadvand ,  Salvatore Frank Pavone ,  Patrick Francis Thompson

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/02317 ,  H01L2224/02331 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03502 ,  H01L2224/03848 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05569 ,  H01L2224/05618 ,  H01L2224/05647 ,  H01L2224/11424 ,  H01L2224/1145 ,  H01L2224/11848 ,  H01L2224/13026 ,  H01L2224/13082 ,  H01L2224/13147 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13618 ,  H01L2224/13647 ,  H01L2924/0132

Abstract: A method for manufacturing a package includes positioning a copper layer above a die. A zinc layer is positioned on the copper layer. The zinc and copper layers are then heated to produce a brass layer, the brass layer abutting the copper layer. Further, a polymer layer is positioned abutting the brass layer.

公开(公告)号：US20230317673A1

公开(公告)日：2023-10-05

申请号：US17710941

申请日：2022-03-31

Applicant: Texas Instruments Incorporated

Inventor： Yiqi Tang ,  Vivek Swaminathan Sridharan ,  Rajen Manicon Murugan ,  Patrick Francis Thompson

IPC: H01L23/00 ,  H01L23/498

CPC classification number: H01L24/73 ,  H01L24/24 ,  H01L24/16 ,  H01L24/20 ,  H01L23/49816 ,  H01L24/17 ,  H01L24/19 ,  H01L2224/73209 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/24226 ,  H01L2224/24246 ,  H01L2924/37001 ,  H01L2924/186 ,  H01L2924/182 ,  H01L2224/2101 ,  H01L2224/2105 ,  H01L2224/17134

Abstract: A described example includes: a reconstituted semiconductor device flip chip mounted on a device side surface of a package substrate, the package substrate having terminals for connecting the package substrate to a circuit board, the reconstituted semiconductor device further including: a semiconductor die mounted in a dielectric layer and having bond pads spaced from one another by at least a first pitch distance that is less than 100 microns; a redistribution layer formed over the bond pads having conductors in passivation layers; solder bumps on the redistribution layer coupled to the bond pads of the semiconductor die, the solder bumps spaced from one another by at least a second pitch distance that is greater than the first pitch distance; and solder joints formed between the package substrate and the solder bumps, the solder joints coupling the package substrate to the semiconductor die in the reconstituted semiconductor device.

公开(公告)号：US11362047B2

公开(公告)日：2022-06-14

申请号：US16850620

申请日：2020-04-16

Applicant: Texas Instruments Incorporated

Inventor： Vivek Swaminathan Sridharan ,  Yiqi Tang ,  Christopher Daniel Manack ,  Rajen Manicon Murugan ,  Liang Wan ,  Hiep Xuan Nguyen

IPC: H01L23/60 ,  H01L23/495 ,  H01L23/00 ,  H01L33/00 ,  H01L33/62 ,  H01L21/683

Abstract: A system in a package (SIP) includes carrier layer regions that have a dielectric material with a metal post therethrough, where adjacent carrier layer regions define a gap. A driver IC die is positioned in the gap having nodes connected to bond pads exposed by openings in a top side of a first passivation layer, with the bond pads facing up. A dielectric layer is on the first passivation layer and carrier layer region that includes filled through vias coupled to the bond pads and to the metal post. A light blocking layer is on sidewalls and a bottom of the substrate. A first device includes a light emitter that has first bondable features. The light blocking layer can block at least 90% of incident light. The first bondable features are flipchip mounted to a first portion of the bond pads.

公开(公告)号：US11978709B2

公开(公告)日：2024-05-07

申请号：US17752037

申请日：2022-05-24

Applicant: Texas Instruments Incorporated

Inventor： Vivek Swaminathan Sridharan ,  Yiqi Tang ,  Christopher Daniel Manack ,  Rajen Manicon Murugan ,  Liang Wan ,  Hiep Xuan Nguyen

IPC: H01L23/60 ,  H01L23/00 ,  H01L23/495 ,  H01L33/00 ,  H01L33/62 ,  H01L21/683 ,  H01L25/16

CPC classification number: H01L23/60 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49575 ,  H01L24/28 ,  H01L24/82 ,  H01L33/005 ,  H01L33/62 ,  H01L21/6835 ,  H01L24/24 ,  H01L24/25 ,  H01L25/167 ,  H01L2933/005 ,  H01L2933/0066

Abstract: A system in a package (SIP) includes carrier layer regions that have a dielectric material with a metal post therethrough, where adjacent carrier layer regions define a gap. A driver IC die is positioned in the gap having nodes connected to bond pads exposed by openings in a top side of a first passivation layer, with the bond pads facing up. A dielectric layer is on the first passivation layer and carrier layer region that includes filled through vias coupled to the bond pads and to the metal post. A light blocking layer is on sidewalls and a bottom of the substrate. A first device includes a light emitter that has first bondable features. The light blocking layer can block at least 90% of incident light. The first bondable features are flipchip mounted to a first portion of the bond pads.