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公开(公告)号:US11600534B2
公开(公告)日:2023-03-07
申请号:US17218459
申请日:2021-03-31
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Wei-Min Liu , Hsueh-Chang Sung , Li-Li Su , Yee-Chia Yeo
IPC: H01L21/8238 , H01L27/092 , H01L29/08 , H01L29/49 , H01L29/78 , H01L29/66
Abstract: A semiconductor device includes a first device region and a second device region. The first device region includes a first source/drain region extending from a substrate and a first and a second pair of spacers. The first source/drain region extends between the first pair of spacers and the second pair of spacers. The first pair of spacers and the second pair of spacers have a first height. The second device region includes a second and a third source/drain region extending from the substrate and a third and a fourth pair of spacers. The third source/drain region is separate from the second source/drain region. The second source/drain region extends between the third pair of spacers. The third source/drain region extends between the fourth pair of spacers. The third pair of spacers and the fourth pair of spacers have a second height greater than the first height.
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公开(公告)号:US20230068434A1
公开(公告)日:2023-03-02
申请号:US17458950
申请日:2021-08-27
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Chien-I Kuo , Wei Hao Lu , Li-Li Su , Yee-Chia Yeo
IPC: H01L29/08 , H01L21/8234 , H01L29/66 , H01L29/78 , H01L29/06
Abstract: A method of forming a semiconductor includes forming a first recess in a first semiconductor fin protruding from a substrate and forming a second recess in a second semiconductor fin protruding from the substrate first semiconductor fin and forming a source/drain region in the first recess and the second recess. Forming the source/drain region includes forming a first portion of a first layer in the first recess and forming a second portion of the first layer in the second recess, forming a second layer on the first layer by flowing a first precursor, and forming a third layer on the second layer by flowing a second precursor, the third layer being a single continuous material.
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公开(公告)号:US20230065620A1
公开(公告)日:2023-03-02
申请号:US17412652
申请日:2021-08-26
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Wei-Min Liu , Li-Li Su , Yee-Chia Yeo
IPC: H01L27/088 , H01L29/78 , H01L29/66 , H01L21/8234
Abstract: An embodiment includes a device including a first fin extending from a substrate. The device also includes a first gate stack over and along sidewalls of the first fin. The device also includes a first gate spacer disposed along a sidewall of the first gate stack. The device also includes and a first source/drain region in the first fin and adjacent the first gate spacer, the first source/drain region including a first carbon-containing buffer layer on the first fin. The device also includes and a first epitaxial structure on the first carbon-containing buffer layer.
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公开(公告)号:US11532750B2
公开(公告)日:2022-12-20
申请号:US16941427
申请日:2020-07-28
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Li-Li Su , Wei-Min Liu , Wei Hao Lu , Chien-I Kuo , Yee-Chia Yeo
IPC: H01L29/78 , H01L29/66 , H01L21/8234
Abstract: A device includes a fin extending from a substrate; a gate stack over and along sidewalls of the fin; a gate spacer along a sidewall of the gate stack; an epitaxial source/drain region in the fin and adjacent the gate spacer, the epitaxial source/drain region including a first epitaxial layer on the fin, the first epitaxial layer including silicon and arsenic; and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer including silicon and phosphorus, the first epitaxial layer separating the second epitaxial layer from the fin; and a contact plug on the second epitaxial layer.
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公开(公告)号:US20220359653A1
公开(公告)日:2022-11-10
申请号:US17644140
申请日:2021-12-14
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Wei-Min Liu , Li-Li Su , Chii-Horng Li , Yee-Chia Yeo
IPC: H01L29/06 , H01L29/423 , H01L29/786 , H01L21/8234
Abstract: A device includes a first nanostructure over a semiconductor substrate; a second nanostructure over the first nanostructure; a gate structure surrounding the first nanostructure and the second nanostructure; a first epitaxial region in the semiconductor substrate adjacent the gate structure, wherein the first epitaxial region is a first doped semiconductor material; and a second epitaxial region over the first epitaxial region, wherein the second epitaxial region is adjacent the first nanostructure and the second nanostructure, wherein the second epitaxial region is a second doped semiconductor material that is different from the first doped semiconductor material. In an embodiment, the first doped semiconductor material has a smaller doping concentration than the second doped semiconductor material.
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公开(公告)号:US20210391324A1
公开(公告)日:2021-12-16
申请号:US16901791
申请日:2020-06-15
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Wei Hao Lu , Yi-Fang Pai , Cheng-Wen Cheng , Li-Li Su , Chien-I Kuo
IPC: H01L27/088 , H01L29/08 , H01L29/167 , H01L21/8234
Abstract: A semiconductor device includes: a first fin and a second fin extending from a substrate and an epitaxial source/drain region. The epitaxial source/drain region includes a first portion grown on the first fin and a second portion grown on the second fin, and the first portion and the second portion are joined at a merging boundary. The epitaxial source/drain region further includes a first subregion extending from a location level with a highest point of the epitaxial source/drain region to a location level with a highest point of the merging boundary, a second subregion extending from the location level with the highest point of the merging boundary to a location level with a lowest point of the merging boundary, and a third subregion extending from the location level with the lowest point of the merging boundary to a location level with the lowest point of the epitaxial source/drain region.
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公开(公告)号:US20190355816A1
公开(公告)日:2019-11-21
申请号:US16531421
申请日:2019-08-05
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Chien-I Kuo , Shao-Fu Fu , Chia-Ling Chan , Yi-Fang Pai , Li-Li Su , Wei Hao Lu , Wei Te Chiang , Chii-Horng Li
IPC: H01L29/08 , H01L29/66 , H01L21/22 , H01L21/02 , H01L29/36 , H01L29/167 , H01L29/78 , H01L21/223
Abstract: The present disclosure relates generally to an epitaxy scheme for forming source/drain regions in a semiconductor device, such as an n-channel device. In an example, a method of manufacturing a semiconductor device includes forming an active area on a substrate. The active area includes a source/drain region. The formation of the source/drain region includes forming a barrier region along a bottom surface and side surface of a recess in the active area. The barrier region includes arsenic having a first dopant concentration. The formation of the source/drain region further includes forming an epitaxial material on the barrier region in the recess. The epitaxial material includes phosphorous having a second dopant concentration.
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公开(公告)号:US10374038B2
公开(公告)日:2019-08-06
申请号:US15922643
申请日:2018-03-15
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Chien-I Kuo , Chii-Horng Li , Chia-Ling Chan , Li-Li Su , Yi-Fang Pai , Wei Te Chiang , Shao-Fu Fu , Wei Hao Lu
IPC: H01L21/8234 , H01L29/08 , H01L29/167 , H01L29/36 , H01L21/223 , H01L21/02 , H01L29/78 , H01L29/66 , H01L21/3065 , H01L21/306
Abstract: The present disclosure relates generally to an epitaxy scheme for forming source/drain regions in a semiconductor device, such as an n-channel device. In an example, a method of manufacturing a semiconductor device includes forming an active area on a substrate. The active area includes a source/drain region. The formation of the source/drain region includes forming a barrier region along a bottom surface and side surface of a recess in the active area. The barrier region includes arsenic having a first dopant concentration. The formation of the source/drain region further includes forming an epitaxial material on the barrier region in the recess. The epitaxial material includes phosphorous having a second dopant concentration.
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