公开(公告)号：US20240405070A1

公开(公告)日：2024-12-05

申请号：US18780842

申请日：2024-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Min Liu ,  Li-Li Su ,  Yee-Chia Yeo

IPC: H01L29/06 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: In an embodiment, a device includes: a first nanostructure; a source/drain region adjoining a first channel region of the first nanostructure, the source/drain region including: a main layer; and a first liner layer between the main layer and the first nanostructure, a carbon concentration of the first liner layer being greater than a carbon concentration of the main layer; an inter-layer dielectric on the source/drain region; and a contact extending through the inter-layer dielectric, the contact connected to the main layer, the contact spaced apart from the first liner layer.

公开(公告)号：US12074071B2

公开(公告)日：2024-08-27

申请号：US18178640

申请日：2023-03-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Min Liu ,  Hsueh-Chang Sung ,  Li-Li Su ,  Yee-Chia Yeo

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823864 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/4983 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device includes a first device region and a second device region. The first device region includes a first source/drain region extending from a substrate and a first and a second pair of spacers. The first source/drain region extends between the first pair of spacers and the second pair of spacers. The first pair of spacers and the second pair of spacers have a first height. The second device region includes a second and a third source/drain region extending from the substrate and a third and a fourth pair of spacers. The third source/drain region is separate from the second source/drain region. The second source/drain region extends between the third pair of spacers. The third source/drain region extends between the fourth pair of spacers. The third pair of spacers and the fourth pair of spacers have a second height greater than the first height.

公开(公告)号：US11677013B2

公开(公告)日：2023-06-13

申请号：US17072418

申请日：2020-10-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Min Liu ,  Li-Li Su ,  Yee-Chia Yeo

IPC: H01L29/66 ,  H01L29/04 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/7851

Abstract: The present disclosure is directed to methods for forming source/drain (S/D) epitaxial structures with a hexagonal shape. The method includes forming a fin structure that includes a first portion and a second portion proximate to the first portion, forming a gate structure on the first portion of the fin structure, and recessing the second portion of the fin structure. The method further includes growing a S/D epitaxial structure on the recessed second portion of the fin structure, where growing the S/D epitaxial structure includes exposing the recessed second portion of the fin structure to a precursor and one or more reactant gases to form a portion of the S/D epitaxial structure. Growing the S/D epitaxial structure further includes exposing the portion of the S/D structure to an etching chemistry and exposing the portion of the S/D epitaxial structure to a hydrogen treatment to enhance growth of the S/D epitaxial structure.

公开(公告)号：US20220367625A1

公开(公告)日：2022-11-17

申请号：US17565716

申请日：2021-12-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Min Liu ,  Li-Li Su ,  Yee-Chia Yeo

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/8234

Abstract: In an embodiment, a device includes: a first nanostructure; a source/drain region adjoining a first channel region of the first nanostructure, the source/drain region including: a main layer; and a first liner layer between the main layer and the first nanostructure, a carbon concentration of the first liner layer being greater than a carbon concentration of the main layer; an inter-layer dielectric on the source/drain region; and a contact extending through the inter-layer dielectric, the contact connected to the main layer, the contact spaced apart from the first liner layer.

公开(公告)号：US20210265195A1

公开(公告)日：2021-08-26

申请号：US17315842

申请日：2021-05-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ru Lee ,  Chii-Horng Li ,  Chien-I Kuo ,  Li-Li Su ,  Chien-Chang Su ,  Heng-Wen Ting ,  Jung-Chi Tai ,  Che-Hui Lee ,  Ying-Wei Li

IPC: H01L21/764 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/24 ,  H01L29/161 ,  H01L29/165 ,  H01L29/78 ,  H01L29/66

Abstract: An embodiment is a structure including a first fin over a substrate, a second fin over the substrate, the second fin being adjacent the first fin, an isolation region surrounding the first fin and the second fin, a gate structure along sidewalls and over upper surfaces of the first fin and the second fin, the gate structure defining channel regions in the first fin and the second fin, a source/drain region on the first fin and the second fin adjacent the gate structure, and an air gap separating the source/drain region from a top surface of the substrate.

公开(公告)号：US12243931B2

公开(公告)日：2025-03-04

申请号：US18311071

申请日：2023-05-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Min Liu ,  Yee-Chia Yeo ,  Li-Li Su

IPC: H01L29/66 ,  H01L29/04 ,  H01L29/08 ,  H01L29/78

Abstract: The present disclosure is directed to methods for forming source/drain (S/D) epitaxial structures with a hexagonal shape. The method includes forming a fin structure that includes a first portion and a second portion proximate to the first portion, forming a gate structure on the first portion of the fin structure, and recessing the second portion of the fin structure. The method further includes growing a S/D epitaxial structure on the recessed second portion of the fin structure, where growing the S/D epitaxial structure includes exposing the recessed second portion of the fin structure to a precursor and one or more reactant gases to form a portion of the S/D epitaxial structure. Growing the S/D epitaxial structure further includes exposing the portion of the S/D structure to an etching chemistry and exposing the portion of the S/D epitaxial structure to a hydrogen treatment to enhance growth of the S/D epitaxial structure.

公开(公告)号：US20240371636A1

公开(公告)日：2024-11-07

申请号：US18777256

申请日：2024-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Min Liu ,  Li-Li Su ,  Yee-Chia Yeo

IPC: H01L21/02 ,  C23C16/02 ,  C23C16/08 ,  C23C16/50 ,  C23C16/56 ,  C30B25/10 ,  C30B25/14 ,  C30B25/18 ,  C30B29/52 ,  H01J37/05 ,  H01J37/32 ,  H01L21/28 ,  H01L21/3065 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

Abstract: A method includes flowing first precursors over a semiconductor substrate to form an epitaxial region, the epitaxial region includes a first element and a second element; converting a second precursor into first radicals and first ions; separating the first radicals from the first ions; and flowing the first radicals over the epitaxial region to remove at least some of the second element from the epitaxial region.

公开(公告)号：US20230369502A1

公开(公告)日：2023-11-16

申请号：US17663165

申请日：2022-05-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shao-Yang Ma ,  Cheng-Yen Wen ,  Li-Li Su ,  Chil-Horng Li ,  Yee-Chia Yeo

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/78618 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/78696 ,  H01L21/02592 ,  H01L21/02667 ,  H01L21/02576 ,  H01L29/66742

Abstract: A semiconductor device including a seeding layer in the source/drain region and a method of forming is provided. The semiconductor device may include a plurality of nanostructures over a substrate, a gate wrapping around the plurality of nanostructures, a source/drain region adjacent the plurality of nanostructures, and inner spacers between the source/drain region and the gate stack. The source/drain region may include a polycrystalline seeding layer covering sidewalls of the plurality of nanostructures and sidewalls of the inner spacers, and a semiconductor layer over the seeding layer. The semiconductor layer may have a higher dopant concentration than the seeding layer.

公开(公告)号：US20220344151A1

公开(公告)日：2022-10-27

申请号：US17238808

申请日：2021-04-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Min Liu ,  Li-Li Su ,  Yee-Chia Yeo

IPC: H01L21/02 ,  H01L21/3065 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786 ,  H01L27/092 ,  H01L29/08 ,  H01L29/165 ,  H01J37/32 ,  H01J37/05 ,  C23C16/50 ,  C23C16/08 ,  C23C16/02 ,  C23C16/56 ,  C30B25/10 ,  C30B25/14 ,  C30B25/18 ,  C30B29/52

Abstract: A method includes flowing first precursors over a semiconductor substrate to form an epitaxial region, the epitaxial region includes a first element and a second element; converting a second precursor into first radicals and first ions; separating the first radicals from the first ions; and flowing the first radicals over the epitaxial region to remove at least some of the second element from the epitaxial region.

公开(公告)号：US20220328660A1

公开(公告)日：2022-10-13

申请号：US17809963

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chiang Chang ,  Ming-Hua Yu ,  Li-Li Su

IPC: H01L29/66 ,  H01L21/20 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/417 ,  H01L29/78

Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin in an n-type Fin Field-Effect (FinFET) region and a p-type FinFET region, respectively, forming a first dielectric fin and a second dielectric fin in the n-type FinFET region and the p-type FinFET region, respectively, forming a first epitaxy mask to cover the second semiconductor fin and the second dielectric fin, performing a first epitaxy process to form an n-type epitaxy region based on the first semiconductor fin, removing the first epitaxy mask, forming a second epitaxy mask to cover the n-type epitaxy region and the first dielectric fin, performing a second epitaxy process to form a p-type epitaxy region based on the second semiconductor fin, and removing the second epitaxy mask. After the second epitaxy mask is removed, a portion of the second epitaxy mask is left on the first dielectric fin.