公开(公告)号：US06717887B1

公开(公告)日：2004-04-06

申请号：US10438928

申请日：2003-05-16

Applicant: Takashi Kono ,  Kiyohiro Furutani

Inventor： Takashi Kono ,  Kiyohiro Furutani

IPC: G11C800

CPC classification number: H03L7/0805 ,  G11C7/22 ,  G11C7/222 ,  H03L7/0812

Abstract: A frequency divider divides a frequency of a DLL clock CLK_P into two, to generate ZCLK_PD0 and ZCLK_PD1. A delay circuit generates ZCLK_PDD0, ZCLK_PDD1 obtained by delaying ZCLK_PD0, ZCLK_PD1 respectively by Tc (=a backward amount of CLK_P with respect to an external clock+a delay amount of an internal clock with respect to the external clock). A frequency division select instruction circuit generates ZSEL0, ZSEL1 based on an internal clock CLK, and ZCLK_PDD0, PDD1. A ZSEL0 shifter circuit generates ZSEL1_D2 including a clock pulse of ZSEL1. A ZCLK_P #2 select circuit selects a clock pulse of ZCLK_PD0 using ZSEL1_D2.

Abstract translation: 分频器将DLL时钟CLK_P的频率分成两个，以产生ZCLK_PD0和ZCLK_PD1。 延迟电路通过将ZCLK_PD0，ZCLK_PD1分别延迟Tc（=相对于外部时钟的相对于外部时钟的内部时钟的延迟量的相对于外部时钟的反向量）而获得的ZCLK_PDD0，ZCLK_PDD1）。 分频选择指令电路基于内部时钟CLK和ZCLK_PDD0，PDD1生成ZSEL0，ZSEL1。 ZSEL0移位器电路产生包含ZSEL1的时钟脉冲的ZSEL1_D2。 ZCLK_P＃2选择电路使用ZSEL1_D2选择ZCLK_PD0的时钟脉冲。

公开(公告)号：US06616713B2

公开(公告)日：2003-09-09

申请号：US09987251

申请日：2001-11-14

Applicant: Mitsunori Sano ,  Takashi Kono ,  Kazunori Watanabe

Inventor： Mitsunori Sano ,  Takashi Kono ,  Kazunori Watanabe

IPC: H01G900

CPC classification number: H01G9/012 ,  Y10T29/417 ,  Y10T29/49254

Abstract: An anode lead 17 extending from a capacitor body 18 of a capacitor element 14 is mounted on a connecting portion 21 of an anode terminal 12 and the anode lead 17 and the connecting portion 21 are welded together by laser light B. The welding operation is performed by laser light B in a state where the anode lead 17 is urged to the connecting portion 21 in a region between said anode lead and said connecting portion. Alternatively, the welding operation is performed by laser light B in a state where a reflection plate having a slot and functioning to reflect reflected laser light is arranged in a region between the connecting portion and the capacitor body while the anode lead is received in said slot.

公开(公告)号：US06570812B2

公开(公告)日：2003-05-27

申请号：US09906668

申请日：2001-07-18

Applicant: Takashi Kono

Inventor： Takashi Kono

IPC: G11C800

CPC classification number: G11C8/18

Abstract: In the case where memory arrays are arranged so as to surround the central region where peripheral circuitry and pads are provided, arranging pads for receiving addresses A0 to A12, BA1 and BA0 in two trains is facilitated. By locating an address latch circuit at an equal distance from each pad train, characteristics of the setup time and hold time can be improved.

公开(公告)号：US06519135B2

公开(公告)日：2003-02-11

申请号：US10140180

申请日：2002-05-08

Applicant: Mitsunori Sano ,  Takashi Kono

Inventor： Mitsunori Sano ,  Takashi Kono

IPC: H01G904

CPC classification number: H01G9/012 ,  H01G9/15 ,  H01G11/48 ,  Y02E60/13

Abstract: A chip capacitor has capacitor component 14 having anode lead 17 and sintered body 21 of a metal having a valve action in which anode lead 17 is embedded so as to project from embedding surface 21a, resin-based insulating film layer 24 containing a white pigment and disposed on the embedding surface of capacitor component 14, water-repellent layer 25 disposed on resin-based insulating film layer 24, anode terminal 12 having a portion bent into joint tongue 31, with anode lead 17 being placed on joint tongue 31, joint tongue 31 and anode lead 17 being welded to each other into anode terminal 12, and antireflection member 34 extending from a proximal end of joint tongue 31 of anode terminal 12 toward sintered body 21. When joint tongue 31 and anode lead 17 are welded to each other by a laser beam, antireflection member 34 prevents the laser beam from being reflected from the welded region.

公开(公告)号：US06426671B1

公开(公告)日：2002-07-30

申请号：US09759318

申请日：2001-01-16

Applicant: Takashi Kono

Inventor： Takashi Kono

IPC: G05F110

CPC classification number: G11C5/147 ,  G05F5/00 ,  H01L2924/0002 ,  H01L2924/00

Abstract: According to a reference voltage generated by a reference voltage generating circuit, a level shift circuit generates a control voltage with its level shifted from the reference voltage by a threshold voltage of a difference detection transistor. According to this control voltage, the difference detection transistor operates in a source follower mode to adjust a charged voltage of a capacitance element according to a voltage level of an internal voltage line. A current is supplied from a current drive circuit to the internal voltage line according to the charged voltage. In this way, an internal voltage is generated having a constant voltage level over a wide temperature range with a small occupying area and a small current consumption.

公开(公告)号：US06320810B1

公开(公告)日：2001-11-20

申请号：US09659832

申请日：2000-09-11

Applicant: Takashi Kono ,  Katsuyoshi Mitsui

Inventor： Takashi Kono ,  Katsuyoshi Mitsui

IPC: G11C700

CPC classification number: G11C5/147 ,  G11C7/22 ,  G11C11/4074

Abstract: A through-current Ic of a comparator circuit is switched in accordance with a response speed required with respect to a current consumption. Additionally, a through-current Is of a shifter circuit, which sends to the comparator circuit an output signal at an appropriate level transmitting a difference between an internal power supply potential Vdd and a reference potential Vref is switched according to the required response speed. When a device is in a standby state requiring a small current consumption in internal power supply potential Vdd, both through-currents Ic and Is are set small so that the whole current consumption can be further reduced.

Abstract translation: 根据相对于电流消耗所需的响应速度来切换比较器电路的直流电流Ic。 此外，根据所需的响应速度来切换向比较器电路发送传递内部电源电位Vdd和参考电位Vref之间的差的适当电平的输出信号的移相器电路Is。 当器件处于需要在内部电源电位Vdd中的小电流消耗的待机状态时，将两个贯通电流Ic和Is设定得较小，从而可以进一步降低整个电流消耗。

公开(公告)号：US06314028B1

公开(公告)日：2001-11-06

申请号：US09755246

申请日：2001-01-08

Applicant: Takashi Kono

Inventor： Takashi Kono

IPC: G11C700

CPC classification number: G11C11/4085 ,  G11C7/065 ,  G11C11/4091

Abstract: The amount of charge supplied to a high level sense power supply line by a level control circuit is monitored. Charge of an equal amount is drawn out from a low level sense power supply line according to the monitoring result. In a memory of a boosted sense ground scheme, the boosted sense ground voltage can be maintained at a predetermined voltage level stably.

Abstract translation: 监视由电平控制电路提供给高电平感测电源线的电量。 根据监测结果，从低电平检测电源线提取相等的电量。 在升压感测接地方案的存储器中，升压的感测接地电压可以稳定地保持在预定的电压电平。

公开(公告)号：US06229753B1

公开(公告)日：2001-05-08

申请号：US09576229

申请日：2000-05-22

Applicant: Takashi Kono ,  Katsuyoshi Mitsui

Inventor： Takashi Kono ,  Katsuyoshi Mitsui

IPC: G11C800

CPC classification number: G11C5/145

Abstract: A Vpp level detecting circuit detects a potential on a Vpp trunk line which is provided commonly to a plurality of memory array banks for supplying a boosted potential thereto, and a boosted potential pump circuit supplies a current to the Vpp trunk line in accordance with a result of the detection. Since the position on the Vpp trunk line where the Vpp level detecting circuit performs the monitoring is substantially equally spaced from the respective memory blocks, an influence caused by an active state of the memory array bank can be suppressed during control of the potential on the Vpp trunk line.

Abstract translation: Vpp电平检测电路检测Vpp干线上的电位，该电位共同提供给多个存储器阵列组，用于向其提供升压电位，并且升压电位泵电路根据结果向Vpp中继线提供电流 的检测。 由于Vpp电平检测电路执行监视的Vpp中继线上的位置与各个存储块基本上相等间隔，所以可以在Vpp的电位的控制期间抑制由存储器阵列组的活动状态引起的影响 干线。

公开(公告)号：US06201437B1

公开(公告)日：2001-03-13

申请号：US09166171

申请日：1998-10-05

Applicant: Takashi Kono ,  Katsuyoshi Mitsui ,  Kiyohiro Furutani

Inventor： Takashi Kono ,  Katsuyoshi Mitsui ,  Kiyohiro Furutani

IPC: G05F110

CPC classification number: G05F1/465 ,  G11C5/143 ,  G11C5/145

Abstract: In order to stably generate a high voltage of a prescribed level, a Vpp detection circuit which is activated in response to an activation signal for comparing the high voltage with a reference voltage is forcibly brought into an active state for a prescribed period under control of an initial control circuit.

Abstract translation: 为了稳定地产生规定电平的高电压，响应用于将高电压与基准电压进行比较的激活信号而被激活的Vpp检测电路在控制下被强制地进入活动状态 初始控制电路。

公开(公告)号：US6055199A

公开(公告)日：2000-04-25

申请号：US176880

申请日：1998-10-21

Applicant: Kei Hamade ,  Kiyohiro Furutani ,  Takashi Kono ,  Mikio Asakura

Inventor： Kei Hamade ,  Kiyohiro Furutani ,  Takashi Kono ,  Mikio Asakura

IPC: G11C29/50 ,  G11C7/00

CPC classification number: G11C29/50 ,  G11C11/401

Abstract: A circuit for supplying a stress to memory cells of a semiconductor memory device having the plurality of the memory cells respectively connected to a word line and a bit line comprises a circuit for generating precharge voltage for bit line, a bit line precharging and equalizing circuit which is connected between said circuit for generating precharge voltage for bit line and said memory cells, a pad connected to the bit line precharging and equalizing circuit for applying a desirable voltage to said memory cells through the corresponding bit lines, and a circuit connected to the circuit for generating precharge voltage for bit line for generating a signal for stopping the operation of said circuit for generating precharge voltage for bit line, whereby cell checker patterns can easily be realized in order to screen out possible failures not only in gate oxide films but also in capacitor dielectrics, storage node junctions or the like by applying an arbitrary stress voltage from the outside of the device.

Abstract translation: 用于向具有分别连接到字线和位线的多个存储单元的半导体存储器件的存储单元提供应力的电路包括用于产生位线的预充电电压的电路，位线预充电和均衡电路， 连接在所述用于产生位线的预充电电压的电路和所述存储单元之间，连接到位线预充电和均衡电路的焊盘，用于通过相应的位线向所述存储器单元施加期望的电压，以及连接到电路的电路 用于产生用于产生用于产生用于产生用于产生位线的预充电电压的所述电路的操作的信号的位线的预充电电压，从而可以容易地实现电池检查器图案，以便不仅在栅极氧化膜中屏蔽可能的故障， 电容器电介质，存储节点结等，从外部施加任意的应力电压 设备侧。