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65 条记录 (耗时 0.02 秒)

    Noisy clock test method and apparatus
    61.
    发明授权
    Noisy clock test method and apparatus 有权
    嘈杂的时钟测试方法和设备

    公开(公告)号：US07293190B2

    公开(公告)日：2007-11-06

    申请号：US10720437

    申请日：2003-11-24

    申请人： Thomas Vogelsang

    发明人： Thomas Vogelsang

    IPC分类号： G06F1/04 ,  G06F1/00 ,  G06F1/12 ,  H03K19/00 ,  H03K19/096

    CPC分类号： H03K5/12 ,  H03K5/1252

    摘要： A clock filter for use in filtering an external clock signal to create an internal clock signal for use by an electronic device is provided. The clock filter receives the external clock signal and sets the internal clock signal high when the external clock signal is above a first threshold and sets the internal clock signal low when the external clock signal is below a second threshold. The clock filter holds the internal clock signal constant for a period of time after the clock transitions.

    摘要翻译： 提供了一种用于对外部时钟信号进行滤波以产生电子设备使用的内部时钟信号的时钟滤波器。 当外部时钟信号高于第一阈值时，时钟滤波器接收外部时钟信号并将内部时钟信号设置为高电平，并且当外部时钟信号低于第二阈值时将内部时钟信号设置为低电平。 时钟滤波器在时钟转换后的一段时间内保持内部时钟信号恒定。

    Sense amplifier for eliminating leakage current due to bit line shorts
    62.
    发明申请
    Sense amplifier for eliminating leakage current due to bit line shorts 有权
    用于消除由于位线短路导致的漏电流的感应放大器

    公开(公告)号：US20060245283A1

    公开(公告)日：2006-11-02

    申请号：US11118036

    申请日：2005-04-29

    申请人： Thomas Vogelsang

    发明人： Thomas Vogelsang

    IPC分类号： G11C7/00

    CPC分类号： G11C11/4094 ,  G11C7/065 ,  G11C7/12 ,  G11C11/4091

    摘要： A sense amplifier comprises a transistor configured to be switched with a column select line to pass a bit line equalization voltage, an array equalize device coupled to the transistor for receiving the bit line equalization voltage, a sense amplifier equalize device, a multiplexer coupled between the sense amplifier equalize device and the array equalize device, and a cross-coupled amplifier latch coupled to the sense amplifier equalize device.

    摘要翻译： 读出放大器包括晶体管，其被配置为与列选择线切换以通过位线均衡电压;耦合到晶体管的阵列均衡器件，用于接收位线均衡电压;读出放大器均衡器件; 读出放大器均衡器件和阵列均衡器件，以及耦合到读出放大器的交叉耦合放大器锁存器来均衡器件。

    Standby current reduction over a process window with a trimmable well bias
    63.
    发明申请
    Standby current reduction over a process window with a trimmable well bias 有权

    公开(公告)号：US20060189082A1

    公开(公告)日：2006-08-24

    申请号：US11402412

    申请日：2006-04-12

    申请人： Thomas Vogelsang

    发明人： Thomas Vogelsang

    IPC分类号： H01L21/336

    CPC分类号： H03K19/0013 ,  H01L27/0925 ,  H01L27/0928 ,  Y10S257/901

    摘要： An integrated circuit device including a plurality of MOSFETs of similar type and geometry is formed on a substrate with an ohmic contact, and an adjustable voltage source on the die utilizing clearable fuses is coupled between the ohmic contact and the sources of the MOSFETs. After die processing, a post-processing test is performed to measure an operating characteristic of the die such as leakage current or switching speed, and an external voltage source is applied and adjusted to control the operating characteristic. The on-die fuses are then cleared to adjust the on-die voltage source to match the externally applied voltage. The operating characteristic may be determined by including a test circuit on the die to exhibit the operating characteristic such as a ring oscillator frequency. This approach to controlling manufacturing-induced device performance variations is well suited to efficient manufacture of small feature-size circuits such as DRAMs.

    Multiple chip semiconductor arrangement having electrical components in separating regions
    64.
    发明授权
    Multiple chip semiconductor arrangement having electrical components in separating regions 失效
    在分离区域中具有电气部件的多芯片半导体布置

    公开(公告)号：US07060529B2

    公开(公告)日：2006-06-13

    申请号：US10841162

    申请日：2004-05-07

    申请人： Manfred Reithinger ,  Mike Killian ,  Gerd Frankowsky ,  Oliver Kiehl ,  Gerhard Mueller ,  Ernst Stahl ,  Hartmud Terletzki ,  Thomas Vogelsang

    发明人： Manfred Reithinger ,  Mike Killian ,  Gerd Frankowsky ,  Oliver Kiehl ,  Gerhard Mueller ,  Ernst Stahl ,  Hartmud Terletzki ,  Thomas Vogelsang

    IPC分类号： H01L21/50 ,  H01L21/30

    CPC分类号： H01L25/18 ,  H01L23/50 ,  H01L23/5382 ,  H01L27/105 ,  H01L27/10894 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor packaging arrangement, or module, includes a printed circuit board having an electrical interconnect thereon and a semiconductor package mounted to the printed circuit board. The semiconductor package includes a fractional portion of a semiconductor wafer having a plurality of integrated circuit chips thereon, such chips being separated by regions in the fractional portion of the wafer. The fractional portion of the wafer has a plurality of electrical contacts electrically connected to the chips. The package also includes a dielectric member having an electrical conductor thereon. The electrical conductor are electrically connected to the plurality of electrical contacts of the plurality of chips to electrically interconnect such plurality of chips with portions of the electrical conductor spanning the regions in the fractional portion of the wafer. A connector is provided for electrically connecting the electrical conductor of the package to the electrical interconnect of the printed circuit board.

    摘要翻译： 半导体封装装置或模块包括其上具有电互连的印刷电路板和安装到印刷电路板的半导体封装。 半导体封装包括其上具有多个集成电路芯片的半导体晶片的分数部分，这些芯片由晶片的分数部分中的区域分隔开。 晶片的分数部分具有电连接到芯片的多个电触点。 封装还包括其上具有电导体的电介质构件。 电导体电连接到多个芯片的多个电触头，以将这些多个芯片与跨越晶片的分数部分中的区域的电导体的部分电互连。 提供一种用于将封装的电导体电连接到印刷电路板的电互连的连接器。