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公开(公告)号：US11627531B2
公开(公告)日：2023-04-11
申请号：US17106109
申请日：2020-11-29
Applicant: Silicon Laboratories, Inc.
Inventor： Sriram Mudulodu
Abstract: A wireless local area network (WLAN) station receiver has a center frequency offset (CFO) estimator and an CFO table with an association between a CFO value from a recently received access point packet for which the station is associated according to 802.11. The receiver performs a comparison between the CFO estimate of the received packet and the CFO value from the CFO database, and powers the receiver down if the comparison exceeds a threshold. The threshold may be an absolute value in parts per million, or may include a time drift compensation component.
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公开(公告)号：US20230099832A1
公开(公告)日：2023-03-30
申请号：US17490255
申请日：2021-09-30
Applicant: Silicon Laboratories Inc.
Inventor： Euisoo Yoo , Arup Mukherji , Rangakrishnan Srinivasan , Vitor Pereira , Zhongda Wang , Sriharsha Vasadi
Abstract: In one embodiment, an integrated circuit includes: a first radio frequency (RF) circuit configured to receive and process a first RF signal having a sub-gigahertz (GHz) frequency to output a first lower frequency signal and to transmit RF signals having the sub-GHz frequency; a second RF circuit configured to receive and process a second RF signal having a frequency of at least substantially 2.4 GHz to output a second lower frequency signal and to transmit RF signals at the at least substantially 2.4 GHz; shared analog circuitry coupled to the first RF circuit and the second RF circuit, the shared analog circuitry to receive at least one of the first RF signal or the second RF signal and output a digital output signal; and a digital circuit coupled to the shared analog circuit, the digital circuit to recover message information from the digital output signal.
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公开(公告)号：US11601133B2
公开(公告)日：2023-03-07
申请号：US17081707
申请日：2020-10-27
Applicant: Silicon Laboratories Inc.
Inventor： Anant Verma
Abstract: A system and method for performing discrete frequency transform including a pair of single-bit analog to digital converters (ADCs), a phase converter, a memory, a discrete frequency transform converter and summation circuitry. The ADCs convert an analog input signal into N pairs of binary in-phase and quadrature component samples each being one of four values at a corresponding one of four phases. The phase converter determines a phase value for each pair of component samples. The memory stores a set of discrete frequency transform coefficient values based on N. The discrete frequency transform converter uses a phase value and a pair of discrete frequency transform coefficient values retrieved from the memory for a selected frequency bin to determine a discrete frequency component for each pair of phase component samples. The summation circuitry sums the corresponding N frequency domain components for determining a frequency domain value for the selected frequency bin.
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公开(公告)号：US20230041647A1
公开(公告)日：2023-02-09
申请号：US17395869
申请日：2021-08-06
Applicant: Silicon Laboratories Inc.
Inventor： Sriram MUDULODU
Abstract: A receiver for OFDM subcarriers has a first mode and a second mode. In the first mode, a tunable system clock is output at a nominal frequency, and in the second mode, the tunable system clock is offset so that a harmonic of the tunable system clock coincides with a particular OFDM subcarrier. The tunable system clock is coupled to a programmable modem PLL clock generator which generates clocks for an A/D converter coupled to a baseband processor which is also coupled to the programmable modem PLL clock generator. The programmable modem PLL clock generator is programmed to maintain a constant output frequency of each output in the first mode and the second mode.
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公开(公告)号：US20230006621A1
公开(公告)日：2023-01-05
申请号：US17363049
申请日：2021-06-30
Applicant: Silicon Laboratories Inc.
Inventor： Ruifeng Sun , Sherry Wu , Michael S. Johnson , Vitor Pereira
Abstract: In one embodiment, a dual-mode power amplifier that can operate in different modes includes: a first pair of metal oxide semiconductor field effect transistors (MOSFETs) to receive and pass a constant envelope signal; a second pair of MOSFETs to receive and pass a variable envelope signal, where first terminals of the first pair of MOSFETs are coupled to first terminals of the second pair of MOSFETs, and second terminals of the first pair of MOSFETs are coupled to. second terminals of the second pair of MOSFETs; and a shared MOSFET stack coupled to the first pair of MOSFETs and the second pair of MOSFETs.
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Patent Agency Ranking
公开(公告)号：US20220416440A1
公开(公告)日：2022-12-29
申请号：US17830548
申请日：2022-06-02
Applicant: Silicon Laboratories Inc.
Inventor： Ádám Süle , Attila Zólomy , Szabolcs Lõrincz , Terry Lee Dickey
Abstract: A printed circuit board having an AoX antenna array and a feeding circuit is disclosed. The AoX antenna array has patch antenna disposed on a top layer of the printed circuit board, while the feeding circuit is disposed on the bottom layer. The signal traces that connect the ports of the antenna unit cells to the antenna selection switches are routed so that all are roughly equal in length with a minimal length of parallel sections between signal traces. Thus, the signal traces in the feeding circuit are created so as to minimize phase difference between signal traces and to minimize coupling. Coplanar waveguides, which utilize blind vias are used to further reduce coupling.
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公开(公告)号：US20220416436A1
公开(公告)日：2022-12-29
申请号：US17356853
申请日：2021-06-24
Applicant: Silicon Laboratories Inc.
Inventor： Attila Zólomy , Adám Süle , Andrea Nagy , Jeffrey Tindle , Pasi Rahikkala , Terry Lee Dickey
Abstract: An antenna array that utilizes ground guard rings and metamaterial structures is disclosed. In certain embodiments, the antenna array is constructed from a plurality of antenna unit cells, wherein each antenna unit cell is identical. The antenna unit cell comprises a top surface, that contains a patch antenna and a ground guard ring. A reactive impedance surface (RIS) layer is disposed beneath the top surface and contains the metamaterial structures. The metamaterial structures are configured to present an inductance to the patch antennas, thereby allowing the patch antennas to be smaller than would otherwise be possible. In some embodiments, the metamaterial structures comprise hollow square frames. An antenna array constructed using this antenna unit cell has less coupling than conventional antenna arrays, which results in better performance. Furthermore, this new antenna array also requires less space than conventional antenna arrays.
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公开(公告)号：US11502883B2
公开(公告)日：2022-11-15
申请号：US17108912
申请日：2020-12-01
Applicant: Silicon Laboratories Inc.
Inventor： Wentao Li , Michael A. Wu , Yan Zhou
Abstract: A mixer in a receiver converts a sounding sequence of alternating ones and zeros to an intermediate frequency signal. A digital mixer converts the intermediate frequency signal to a baseband signal that contains a positive tone and a negative tone. A frequency offset correction circuit generates frequency offset corrections based on frequency offset estimates of the frequency offset between a transmitter of the sounding sequence and the receiver. A frequency adjustment circuit adjusts a frequency of the mixer or the digital mixer to thereby center the positive tone and the negative tone around DC. DFT circuits perform single bin DFTs respectively centered on the positive and negative tones. Phases of the positive and negative tones are calculated based on outputs of the DFT circuits and the phases are used to determine fractional time value associated with a distance measurement between the transmitter and receiver.
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69.发明申请公开(公告)号：US20220341989A1
公开(公告)日：2022-10-27
申请号：US17241164
申请日：2021-04-27
Applicant: Silicon Laboratories Inc.
Inventor： Wenshui Zhang , Wei Jue Lim
Abstract: A test system for high voltage testing of semiconductor devices including at least one test socket and a docking plate assembly. Each test socket includes a socket enclosure for encompassing first and second contact finger assemblies, in which the socket enclosure may include a cover and alignment plate. At least one test socket is embedded within the docking plate assembly which is configured to mount between high voltage test head and a pick and place handler. The docking plate assembly and each test socket includes one or more site openings each for receiving a corresponding device under test (DUT) during a high voltage test procedure. Each contact finger assembly includes at least one contact finger configured as an elongated conductor with a bent tip for electrically interfacing a pad of the DUT.
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公开(公告)号：US20220326725A1
公开(公告)日：2022-10-13
申请号：US17847404
申请日：2022-06-23
Applicant: Silicon Laboratories Inc.
Inventor： RICKY SETIAWAN , HUA BENG CHAN , REX TAK YING WONG
Abstract: In an embodiment, an apparatus includes: an amplifier to compare a reference voltage to a feedback voltage and to output a comparison signal based on the comparison; a first loop circuit coupled to the amplifier to receive the comparison signal and output a first feedback voltage for the amplifier to use as the feedback voltage in a first mode of operation; and a second loop circuit coupled to the amplifier. The second loop circuit may be configured to receive the comparison signal and output a second feedback voltage for the amplifier to use as the feedback voltage in a second mode of operation. The second feedback voltage may be greater than the first feedback voltage, and the second loop circuit may output a regulated voltage based on the comparison signal.
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