公开(公告)号：US20030115234A1

公开(公告)日：2003-06-19

申请号：US10136170

申请日：2002-05-01

发明人： Yosef Stein ,  Haim Primo ,  Yaniv Sapir

IPC分类号： G06F007/00

CPC分类号： G06F7/724

摘要： A reconfigurable input Galois field linear transformer system includes a Galois field linear transformer including a matrix of cells; a plurality of storage planes for storing control patterns representing a number of different functions; a storage plane selector circuit for selecting a storage plane representing a function for enabling the cells of the matrix which defines that function; and a reconfigurable input circuit for delivering input data to the enabled cells to apply that function to the input data.

摘要翻译： 可重构输入伽罗瓦域线性变压器系统包括包含单元矩阵的伽罗瓦域线性变换器; 多个存储平面，用于存储表示多个不同功能的控制模式; 存储平面选择器电路，用于选择表示用于使能定义该功能的矩阵的单元的功能的存储平面; 以及可重配置输入电路，用于将输入数据传送到使能小区，以将该功能应用于输入数据。

公开(公告)号：US20030093450A1

公开(公告)日：2003-05-15

申请号：US09973617

申请日：2001-10-09

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Chin-Long Chen

IPC分类号： G06F007/00

CPC分类号： G06F7/724

摘要： Finite field elements from the field GF(2k) are represented as polynomials with binary valued coefficients. As such, multiplication in the field is defined modulo an irreducible polynomial of degree knull1. One of the multiplicands is treated in blocks of polynomials of degree nnull1 so that the multiplier operates over T cycles where knullnT. If k is not a composite number to start with, higher order terms are added, so that multipliers are now constructable even when k is prime. Since n

摘要翻译： 来自场GF（2k）的有限域元素被表示为具有二进制值系数的多项式。 因此，场中的乘法被定义为模k-1的不可约多项式。 被乘数中的一个被处理为具有度数n-1的多项式的块，使得乘数在k = nT的T个周期上操作。 如果k不是开始的复合数，则添加更高阶项，因此即使k是素数，乘法器现在也可构建。 由于n

公开(公告)号：US20030068037A1

公开(公告)日：2003-04-10

申请号：US09974176

申请日：2001-10-10

申请人： STMicroelectronics S.r.I.

发明人： Guido Bertoni ,  Luca Breveglieri ,  Pasqualina Fragneto

IPC分类号： H04L009/00

CPC分类号： G06F7/724

摘要： A circuit for computing the inner of scalar product of two vectors in a finite Galois field defined by a generator polynomial, wherein each vector includes at least two elements belonging to said finite field, comprises one or more look-up tables storing digital words indicative of said possible combinations and said possible reductions. The digital words in question are defined as a function of the second elements of said vectors and the generator polynomial of the field. The input register(s) and the look-up table(s) are configured to co-operate in a plurality of subsequent steps to generate at each step a partial product result identified by at least one of digital word addressed in a corresponding look-up table as a function of the digital signals stored in the input register(s). The circuit also includes an accumulator unit for adding up the partial results generated at each step to give a final product result deriving from accumulation of said partial results.

摘要翻译： 一种用于计算由生成多项式定义的有限伽罗瓦域中的两个向量的标量积的内部的电路，其中每个向量包括属于所述有限域的至少两个元素，包括一个或多个查找表，其存储指示 说可能的组合和所述可能的减少。 所讨论的数字词被定义为所述向量的第二元素和场的生成多项式的函数。 输入寄存器和查找表被配置为在多个后续步骤中协作以在每个步骤处生成由相应查找表中寻址的数字字中的至少一个标识的部分乘积结果， 作为存储在输入寄存器中的数字信号的函数。 该电路还包括用于将在每个步骤产生的部分结果相加以产生从所述部分结果的积累得到的最终产品结果的累加器单元。

公开(公告)号：US06526427B1

公开(公告)日：2003-02-25

申请号：US09455001

申请日：1999-12-06

申请人： Alexander Chiskis ,  Dotan Sokolov ,  Doron Rainish

发明人： Alexander Chiskis ,  Dotan Sokolov ,  Doron Rainish

IPC分类号： G06F102

CPC分类号： G06F7/724 ,  G06F7/584 ,  G06F2207/582

摘要： A method for calculating the mask for an arbitrary delay of a pseudo-noise sequence uses only XOR operations on previously calculated masks. A method for calculating the mask for an arbitrary delay of a pseudo-noise sequence whose shift register polynomial is of order R uses no more than NOP operations where NOP is independent of the delay and NOP is on the order of R.

摘要翻译： 用于计算伪噪声序列的任意延迟的掩模的方法仅对先前计算的掩模使用XOR运算。 用于计算移位寄存器多项式为阶数R的伪噪声序列的任意延迟的掩模的方法不仅使用NOP与延迟无关的NOP操作，并且NOP在R的量级上。

公开(公告)号：US06523054B1

公开(公告)日：2003-02-18

申请号：US09437473

申请日：1999-11-10

申请人： Shunsuke Kamijo

发明人： Shunsuke Kamijo

IPC分类号： G06F772

CPC分类号： G06F7/724

摘要： A practical Galois field arithmetic processor capable of high-speed operation with a simple configuration is disclosed. The processor comprises an instruction decoder, an arithmetic unit including a Galois field vector adder, a Galois field vector multiplier and a Galois exponent adder-subtractor for executing the Galois field arithmetic operation on first and second operands. In the case where the arithmetic unit includes at least a Galois field vector adder and a Galois field vector multiplier, an exponent-vector conversion circuit is provided for converting the second operand from an exponential expression into a vectorial expression, and an instruction is provided for performing the Galois field operation on the vectorially expressed first operand and the exponentially expressed second operand. With this configuration, in the case where the vectorially expressed data is input as the first operand and the exponentially expressed data is input as the second operand, the second operand is converted into a vectorial expression by the conversion circuit, after which the arithmetic operation is performed in the Galois field vector adder or the Galois vector multiplier.

摘要翻译： 公开了一种能够以简单配置进行高速操作的实用的伽罗瓦域算术处理器。 处理器包括指令解码器，包括伽罗瓦域向量加法器，伽罗瓦域向量乘法器和用于在第一和第二操作数上执行伽罗瓦域算术运算的伽罗瓦指数加法器 - 减法器的运算单元。 在运算单元至少包括伽罗瓦域向量加法器和伽罗瓦域向量乘法器的情况下，提供指数矢量转换电路，用于将第二操作数从指数表达式转换为矢量表达式，并且提供指令 对矢量表达的第一操作数和指数表达的第二操作数执行Galois场操作。 利用这种配置，在将第二操作数作为第一操作数输入向量表达数据并且将指数表达数据作为第二操作数输入的情况下，通过转换电路将第二操作数转换为向量表达式，之后算术运算为 在伽罗瓦域矢量加法器或Galois矢量乘法器中执行。

公开(公告)号：US06509728B1

公开(公告)日：2003-01-21

申请号：US09314346

申请日：1999-05-19

申请人： Masaharu Uchino ,  Takashi Shinozuka ,  Haruhiko Hosoya

发明人： Masaharu Uchino ,  Takashi Shinozuka ,  Haruhiko Hosoya

IPC分类号： G01R2316

CPC分类号： G06F7/724 ,  G01R23/16 ,  G06F7/584 ,  G06F7/729 ,  H03K23/54

摘要： A spectrum analyzer including a signal receiving and processing unit, a sampling unit, a histogram measuring unit, an arithmetic unit and a display unit. The signal receiving and processing unit receives an input signal according to the desired frequency sweep information. The sampling unit samples a signal output from receiving and processing unit, according to a plurality of threshold values and outputs a plurality of output codes corresponding to sample values of the envelope of the input signal. The histogram measuring unit measures a group of histograms corresponding to the output codes produced by the sampling unit. The arithmetic unit calculates the amplitude probability distribution (APD) of the output signal based on the histograms. The display unit displays a band group having a plurality of the ranges calculated by the arithmetic unit as an area in different states.

摘要翻译： 一种包括信号接收和处理单元，采样单元，直方图测量单元，运算单元和显示单元的频谱分析仪。 信号接收和处理单元根据期望的频率扫描信息接收输入信号。 采样单元根据多个阈值对从接收和处理单元输出的信号进行采样，并输出与输入信号的包络的采样值对应的多个输出代码。 直方图测量单元测量与采样单元产生的输出代码相对应的一组直方图。 算术单元基于直方图计算输出信号的幅度概率分布（APD）。 显示单元将具有由算术单元计算出的多个范围的频带组显示为不同状态的区域。

公开(公告)号：US20020184281A1

公开(公告)日：2002-12-05

申请号：US09843802

申请日：2001-04-30

发明人： Oscal Tzyh-Chiang Chen ,  Yuh-Feng Hsu

IPC分类号： G06F007/00

CPC分类号： G06F7/724

摘要： A general finite-field multiplier and the method of the same are disclosed for the operation of the finite-field multipliers of various specifications. In the multiplier, AND gates and XOR gates are used as primary components, and the inputs include two elements A and B to be multiplied and the coefficients of a variable polynomial p(x). This multiplier can be applied to the finite-field elements of different bit number. After all the coefficients of the A, B and p(x) are input, the values of a desired C can be obtained rapidly. Since the output values are parallel output, the application is very convenient. Furthermore, the multiplier can be used in the RS chip for different specifications.

摘要翻译： 公开了用于各种规格的有限域乘法器的操作的通用有限域乘法器及其方法。 在乘法器中，AND门和XOR门用作主要组件，并且输入包括要乘以的两个​​元素A和B以及可变多项式p（x）的系数。 该乘法器可以应用于不同位数的有限域元素。 在输入所有A，B和P（x）的系数之后，可以快速获得期望的C值。 由于输出值为并行输出，因此应用非常方便。 此外，乘法器可用于RS芯片中的不同规格。

公开(公告)号：US06459722B2

公开(公告)日：2002-10-01

申请号：US09729037

申请日：2000-12-04

申请人： Sundararajan Sriram ,  Zhenguo Gu

发明人： Sundararajan Sriram ,  Zhenguo Gu

IPC分类号： H04L2730

CPC分类号： H04J13/0022 ,  G06F7/584 ,  G06F7/724 ,  H04J13/10

摘要： A circuit is designed with a plurality of logic circuits (370-374) for producing an offset state matrix. The circuit includes a first logic circuit (380-383) coupled to receive N elements of a respective row of a transition matrix and N elements of column of an input state matrix. The first logic circuit produces a multi-bit logical combination of corresponding bits of the respective row and the column. A second logic circuit (390) is coupled to receive the multi-bit logical combination and produces a respective element of the offset state matrix.

摘要翻译： 电路设计有多个用于产生偏移状态矩阵的逻辑电路（370-374）。 电路包括耦合以接收转移矩阵的相应行的N个元素和输入状态矩阵的列的N个元素的第一逻辑电路（380-383）。 第一逻辑电路产生相应行和列的相应位的多位逻辑组合。 第二逻辑电路（390）被耦合以接收多位逻辑组合并产生偏移状态矩阵的相应元素。

公开(公告)号：US20020136402A1

公开(公告)日：2002-09-26

申请号：US10023934

申请日：2001-12-21

发明人： Scott A. Vanstone

IPC分类号： H04L009/00

CPC分类号： G06F9/30014 ,  G06F7/72 ,  G06F7/722 ,  G06F7/724 ,  G06F7/725 ,  G06F9/30036 ,  G06F2207/382

摘要： The present disclosure provides an arithmetic processor comprising: an arithmetic logic unit having a plurality of arithmetic circuits each for performing a group of associated arithmetic operations, such as finite field operations, or modular integer operations. The arithmetic logic unit has an operand input data bus, for receiving operand data thereon and a result data output bus for returning the results of the arithmetic operations thereon. A register file is coupled to the operand data bus and the result data bus. The register file is shared by the plurality of arithmetic circuits. Further a controller is coupled to the ALU and the register file, the controller selecting one of the plurality of arithmetic circuits in response to a mode control signal requesting an arithmetic operation and for controlling data access between the register file and the ALU and whereby the register file is shared by the arithmetic circuits.

摘要翻译： 本公开提供了一种算术处理器，包括：具有多个算术电路的算术逻辑单元，每个运算电路用于执行一组相关联的算术运算，例如有限场运算或模数整数运算。 算术逻辑单元具有用于在其上接收操作数数据的操作数输入数据总线和用于返回其上的算术运算结果的结果数据输出总线。 寄存器文件耦合到操作数数据总线和结果数据总线。 寄存器文件由多个运算电路共享。 此外，控制器耦合到ALU和寄存器文件，控制器响应于请求算术运算的模式控制信号和用于控制寄存器文件和ALU之间的数据访问来选择多个运算电路中的一个，由此寄存器 文件由算术电路共享。

公开(公告)号：US20020116428A1

公开(公告)日：2002-08-22

申请号：US09788684

申请日：2001-02-21

发明人： Morten Stribaek ,  Kevin D. Kissell ,  Pascal Paillier

IPC分类号： G06F007/38

CPC分类号： G06F7/724 ,  G06F7/725

摘要： Polynomial arithmetic instructions are provided in an instruction set architecture (ISA). A multiply-add-polynomial (MADDP) instruction and a multiply-polynomial (MULTP) instruction are provided.

摘要翻译： 多项运算指令在指令集架构（ISA）中提供。 提供乘法加法多项式（MADDP）指令和乘法多项式（MULTP）指令。