公开(公告)号：US20150236879A1

公开(公告)日：2015-08-20

申请号：US14701160

申请日：2015-04-30

申请人： Sony Corporation

发明人： Samuel Asanbeng ATUNGSIRI ,  Matthew Paul Athol Taylor ,  John Nicholas Wilson

IPC分类号： H04L27/26 ,  H04L5/00 ,  H04L1/00

CPC分类号： H04L5/0007 ,  G11C19/00 ,  H03M13/276 ,  H04L1/0071 ,  H04L5/0053 ,  H04L27/14 ,  H04L27/2602 ,  H04L27/2647

摘要： A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.

摘要翻译： 数据处理装置将要传送的输入符号映射到正交频分复用（OFDM）符号的预定数量的副载波信号。 数据处理器包括交织器存储器，其读入预定数量的数据符号以映射到OFDM子载波信号上。 交织器存储器将数据符号读出到OFDM子载波上以实现映射，读出的顺序与读入不同，顺序是从一组地址确定的，其效果是 数据符号被交织在子载波信号上。 地址集合由包括线性反馈移位寄存器和置换电路的地址发生器产生。

公开(公告)号：US09003243B2

公开(公告)日：2015-04-07

申请号：US11192788

申请日：2005-07-29

申请人： Michael Mao Wang ,  Fuyun Ling ,  Murali Ramaswamy Chari ,  Rajiv Vijayan

发明人： Michael Mao Wang ,  Fuyun Ling ,  Murali Ramaswamy Chari ,  Rajiv Vijayan

IPC分类号： G06F11/00 ,  G11C29/00 ,  H03M13/00 ,  H03M7/00 ,  H04L1/00 ,  H03M13/27 ,  H04L5/00 ,  H04L25/02 ,  H04L27/26

CPC分类号： H04L1/0071 ,  H01R24/38 ,  H03M13/27 ,  H03M13/271 ,  H03M13/2757 ,  H03M13/276 ,  H03M13/2771 ,  H04L1/00 ,  H04L1/0041 ,  H04L1/0066 ,  H04L1/007 ,  H04L5/0007 ,  H04L5/0042 ,  H04L5/0044 ,  H04L5/0048 ,  H04L5/0083 ,  H04L25/0226 ,  H04L27/2607 ,  H04L27/261 ,  H04L27/2626 ,  H04L27/2656 ,  H04L27/2662

摘要： A system and method for modulation diversity uses interleaving. Code bits are placed into groups and are then shuffled within each group.

摘要翻译： 用于调制分集的系统和方法使用交织。 代码位被放置成组，然后在每个组内进行混洗。

公开(公告)号：US20150049838A1

公开(公告)日：2015-02-19

申请号：US14531236

申请日：2014-11-03

申请人： Sony Corporation

发明人： Samuel Asanbeng ATUNGSIRI ,  Matthew Paul Athol Taylor ,  John Nicholas Wilson

IPC分类号： H04L27/26 ,  H04L5/00 ,  H04L1/00

CPC分类号： H04L5/0007 ,  G11C19/00 ,  H03M13/276 ,  H04L1/0071 ,  H04L5/0053 ,  H04L27/14 ,  H04L27/2602 ,  H04L27/2647

摘要： A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.

公开(公告)号：US08891691B2

公开(公告)日：2014-11-18

申请号：US14078159

申请日：2013-11-12

申请人： Sony Corporation

发明人： Samuel Asanbeng Atungsiri ,  Matthew Paul Athol Taylor ,  John Nicholas Wilson

IPC分类号： H04L27/06 ,  H04L1/00 ,  H04L27/14 ,  H04L5/00

CPC分类号： H04L5/0007 ,  G11C19/00 ,  H03M13/276 ,  H04L1/0071 ,  H04L5/0053 ,  H04L27/14 ,  H04L27/2602 ,  H04L27/2647

摘要： A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.

摘要翻译： 数据处理装置将要传送的输入符号映射到正交频分复用（OFDM）符号的预定数量的副载波信号。 数据处理器包括交织器存储器，其读入预定数量的数据符号以映射到OFDM子载波信号上。 交织器存储器将数据符号读出到OFDM子载波上以实现映射，读出的顺序与读入不同，顺序是从一组地址确定的，其效果是 数据符号被交织在子载波信号上。 地址集合由包括线性反馈移位寄存器和置换电路的地址发生器产生。

公开(公告)号：US08787145B2

公开(公告)日：2014-07-22

申请号：US13608320

申请日：2012-09-10

申请人： Philip Treigherman

发明人： Philip Treigherman

IPC分类号： H04L27/28 ,  H04L1/00 ,  H04L27/26 ,  H03M13/27

CPC分类号： H04L27/2647 ,  H03M13/2732 ,  H03M13/276 ,  H03M13/2789 ,  H04L1/0052 ,  H04L1/0071

摘要： A method and apparatus for de-interleaving interleaved data in a deinterleaver memory in an Orthogonal Frequency Division Multiplexing (OFDM) based Integrated Services Digital Broadcasting Terrestrial (ISDB-T) receiver. In different embodiments, the apparatus comprises of a OFDM symbol counter along with a divider or a buffer pointer RAM with circular pointer logic, a first lookup table to obtain delay buffer size and interleaving lengths for a given OFDM transmission layer, and a second lookup table to obtain buffer base address and interleaving lengths for a given OFDM transmission layer.

摘要翻译： 一种用于在基于正交频分复用（OFDM）的综合业务数字广播地面（ISDB-T）接收机中的解交织器存储器中对交错数据进行解交织的方法和装置。 在不同的实施例中，该装置包括OFDM符号计数器以及具有循环指针逻辑的分频器或缓冲器指针RAM，用于获得给定OFDM传输层的延迟缓冲器大小和交织长度的第一查找表和第二查找表 以获得给定OFDM传输层的缓冲器基址和交织长度。

公开(公告)号：US08671324B2

公开(公告)日：2014-03-11

申请号：US13668665

申请日：2012-11-05

申请人： The DIRECTV Group, Inc.

发明人： Mustafa Eroz ,  A. Roger Hammons, Jr. ,  Feng-Wen Sun

IPC分类号： H03M13/00

CPC分类号： H03M13/271 ,  H03M13/2735 ,  H03M13/2746 ,  H03M13/276 ,  H03M13/2767 ,  H03M13/2771 ,  H03M13/2789 ,  H03M13/2957

摘要： A method of interleaving blocks of indexed data of varying lengths is disclosed. The method includes the steps of: providing a set of basic Interleavers comprising a family of one or more permutations of the indexed data and having a variable length; selecting one of the basic Interleavers based upon a desired Interleaver length L; and adapting the selected basic Interleaver to produce an Interleaver having the desired Interleaver length L.

摘要翻译： 公开了一种交织不同长度的索引数据块的方法。 该方法包括以下步骤：提供一组基本交错器，其包括索引数据的一个或多个排列的族，并具有可变长度; 基于所需的交织器长度L选择基本交织器之一; 并且使所选择的基本交织器适配以产生具有期望的交织器长度L的交织器。

公开(公告)号：US20140068168A1

公开(公告)日：2014-03-06

申请号：US13794796

申请日：2013-03-12

申请人： IMAGINATION TECHNOLOGIES LIMITED

发明人： Paul Murrin ,  Adrian J. Anderson ,  Mohammed El-Hajjar

IPC分类号： G06F12/06

CPC分类号： G06F12/0607 ,  H03M13/2707 ,  H03M13/276 ,  H03M13/6505

摘要： Tile based interleaving and de-interleaving of row-column interleaved data is described. In one example, the de-interleaving is divided into two memory transfer stages, the first from an on-chip memory to a DRAM and the second from the DRAM to an on-chip memory. Each stage operates on part of a row-column interleaved block of data and re-orders the data items, such that the output of the second stage comprises de-interleaved data. In the first stage, data items are read from the on-chip memory according to a non-linear sequence of memory read addresses and written to the DRAM. In the second stage, data items are read from the DRAM according to bursts of linear address sequences which make efficient use of the DRAM interface and written back to on-chip memory according to a non-linear sequence of memory write addresses.

摘要翻译： 描述了基于平铺的交错和行交错数据的解交织。 在一个示例中，解交织被分为两个存储器传送级，第一级从片上存储器到DRAM，第二级从DRAM到片上存储器。 每个阶段在行列交织的数据块的一部分上进行操作，并重新命令数据项，使得第二级的输出包括解交织的数据。 在第一阶段，根据存储器读取地址的非线性序列从片上存储器读取数据项并写入DRAM。 在第二阶段中，根据线性地址序列的突发从DRAM读出数据项，这些片段有效利用DRAM接口，并根据存储器写地址的非线性序列写回到片上存储器。

公开(公告)号：US08619890B2

公开(公告)日：2013-12-31

申请号：US13615732

申请日：2012-09-14

申请人： Samuel Asanbeng Atungsiri ,  Matthew Paul Athol Taylor ,  John Nicholas Wilson

发明人： Samuel Asanbeng Atungsiri ,  Matthew Paul Athol Taylor ,  John Nicholas Wilson

IPC分类号： H04K1/10

CPC分类号： H04L5/0007 ,  G11C19/00 ,  H03M13/276 ,  H04L1/0071 ,  H04L5/0053 ,  H04L27/14 ,  H04L27/2602 ,  H04L27/2647

摘要： A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.

摘要翻译： 数据处理装置将要传送的输入符号映射到正交频分复用（OFDM）符号的预定数量的副载波信号。 数据处理器包括交织器存储器，其读入预定数量的数据符号以映射到OFDM子载波信号上。 交织器存储器将数据符号读出到OFDM子载波上以实现映射，读出的顺序与读入不同，顺序是从一组地址确定的，其效果是 数据符号被交织在子载波信号上。 地址集合由包括线性反馈移位寄存器和置换电路的地址发生器产生。

公开(公告)号：US08527833B2

公开(公告)日：2013-09-03

申请号：US13231474

申请日：2011-09-13

申请人： Rohit Seshadri ,  Mustafa Eroz ,  Lin-Nan Lee

发明人： Rohit Seshadri ,  Mustafa Eroz ,  Lin-Nan Lee

IPC分类号： H03M13/00

CPC分类号： H03M13/2767 ,  H03M13/275 ,  H03M13/276 ,  H03M13/2789

摘要： A parameterized interleaver design process is provided, which optimizes the design for interleavers of any size, and can be completely specified using only a few design parameters. According to the parameterized interleaver design process an interleaver π(i) of a length N is generated. A number of subpermutation masks are defined, and a first intermediate interleaver permutation is partitioned into a number of subgroups, wherein the number of subgroups corresponds with the number of subpermutation masks. Each of the subgroups of the first intermediate interleaver permutation is partitioned into a number of further subgroups, and each of the subpermutation masks is applied to each of the further subgroups of a corresponding subgroup of the first intermediate interleaver permutation, resulting in a corresponding portion of a second intermediate interleaver permutation. The resulting interleaver π(i) is generated based at least in part on the first and second intermediate interleaver permutations.

摘要翻译： 提供了一种参数化的交织器设计过程，其优化了任何尺寸的交织器的设计，并且可以仅使用少量设计参数来完全指定。 根据参数化交织器设计处理，生成长度为N的交织器pi（i）。 定义了多个子鉴别掩码，并且将第一中间交织器置换分割成多个子组，其中子组的数量对应于子鉴别掩码的数量。 第一中间交织器排列的每个子组被划分成多个其他子组，并且每个子质量掩模被应用于第一中间交织器排列的相应子组的其他子组中的每一个，导致相应部分 第二中间交织器排列。 至少部分地基于第一和第二中间交织器排列来生成所产生的交织器pi（i）。

公开(公告)号：US08429510B2

公开(公告)日：2013-04-23

申请号：US12912147

申请日：2010-10-26

申请人： Shai Kalfon ,  Moshe Bukris

发明人： Shai Kalfon ,  Moshe Bukris

IPC分类号： H03M13/00

CPC分类号： H03M13/276 ,  H03M13/2739 ,  H03M13/2775

摘要： An apparatus including a first circuit and a second circuit. The first circuit may be configured to store a block of data values arranged in a first order. The first circuit may be further configured to present a plurality of the data values in parallel in response to a plurality of address signals, where the data values are presented in a second order. The second circuit may be configured to generate the plurality of address signals in response to a first signal, a second signal and a third signal. The second circuit generally includes an even number of address generators configured to generate the plurality of address signals in parallel.

摘要翻译： 一种包括第一电路和第二电路的装置。 第一电路可以被配置为存储以一级排列的数据值块。 第一电路可以被进一步配置为响应于多个地址信号并行地呈现多个数据值，其中数据值以二次呈现。 第二电路可以被配置为响应于第一信号，第二信号和第三信号而产生多个地址信号。 第二电路通常包括偶数个地址发生器，其被配置为并行地生成多个地址信号。