公开(公告)号：USD608715S1

公开(公告)日：2010-01-26

申请号：US29338457

申请日：2009-06-11

Applicant: George Bucher ,  Melvin Betancourt ,  James Yu-Hsin Kuo

Designer： George Bucher ,  Melvin Betancourt ,  James Yu-Hsin Kuo

公开(公告)号：US20090058436A1

公开(公告)日：2009-03-05

申请号：US11849336

申请日：2007-09-03

Applicant: James Yu

Inventor： James Yu

IPC: G01R27/02

CPC classification number: G01R27/04 ,  H04L12/10

Abstract: A system and method for measuring a cable resistance in a power over Ethernet (PoE) application. A short circuit module in a powered device is designed to produce a short circuit effect upon receipt of a cable resistance detection voltage. The cable resistance detection voltage can be designed to be greater than a voltage for detection or classification and less than a voltage for powering of the powered device. The measurement of the current at a time when a short circuit effect is produced at the powered device enables a calculation of the actual resistance of the cable on a given PoE port.

Abstract translation: 一种用于测量以太网供电（PoE）应用中的电缆电阻的系统和方法。 被动设备中的短路模块被设计成在接收到电缆电阻检测电压时产生短路效应。 电缆电阻检测电压可以被设计为大于用于检测或分类的电压，并且小于用于供电设备供电的电压。 电源设备产生短路效应时电流的测量可以计算给定PoE端口电缆的实际电阻。

公开(公告)号：US20050257010A1

公开(公告)日：2005-11-17

申请号：US11066038

申请日：2005-02-25

Applicant: Phillip Jones ,  Paras Shah ,  James Yu ,  William Walker ,  Kenneth Jansen ,  Vasileios Balabanos ,  Andrew Olsen

Inventor： Phillip Jones ,  Paras Shah ,  James Yu ,  William Walker ,  Kenneth Jansen ,  Vasileios Balabanos ,  Andrew Olsen

IPC: G06F12/00 ,  G06F12/08

CPC classification number: G06F12/0813 ,  G06F2212/2542

Abstract: A system comprises a plurality of nodes coupled together via a switching device. Each node comprises a processor coupled to a memory. Migration logic in the switching device is configured to migrate segments of each memory to the switching device.

Abstract translation: 系统包括通过交换设备耦合在一起的多个节点。 每个节点包括耦合到存储器的处理器。 交换设备中的迁移逻辑被配置为将每个存储器的段迁移到交换设备。

公开(公告)号：US06404864B1

公开(公告)日：2002-06-11

申请号：US09326927

申请日：1999-06-05

Applicant: Tom Evslin ,  Edward Hirschman ,  Jay Meranchik ,  James Yu

Inventor： Tom Evslin ,  Edward Hirschman ,  Jay Meranchik ,  James Yu

IPC: H04M1500

CPC classification number: H04L65/104 ,  H04L29/06 ,  H04L29/06027 ,  H04L65/103 ,  H04L65/80 ,  H04M3/2227 ,  H04M3/367 ,  H04M7/1285 ,  H04M15/30 ,  H04M15/49 ,  H04M15/56 ,  H04M15/58 ,  H04M15/745 ,  H04M15/8016 ,  H04M15/8044 ,  H04M15/8083 ,  H04M2215/0108 ,  H04M2215/0168 ,  H04M2215/0184 ,  H04M2215/0188 ,  H04M2215/202 ,  H04M2215/42 ,  H04M2215/46 ,  H04M2215/7414 ,  H04M2215/745 ,  H04M2215/92 ,  H04Q3/0062

Abstract: In some embodiments, the present invention provides a distributed monitoring, evaluation and routing (“DiMER”) system that provides active management of a data-network based telephony networks. Such a system, and data-network-based telephony networks incorporating the same, advantageously route calls to meet call-quality standards and/or cost goals, among other targets. To meet such quality standards, the system periodically obtains call-related data, analyzes the data, and revises call routing, as appropriate, by shifting or reallocating call traffic between available terminating gateways (based on their performance).

Abstract translation: 在一些实施例中，本发明提供了分布式监控，评估和路由（“DiMER”）系统，其提供基于数据网络的电话网络的主动管理。 这样的系统以及包含该系统的基于数据网络的电话网络有利地路由呼叫以满足呼叫质量标准和/或成本目标以及其他目标。 为了满足这样的质量标准，系统可以通过在可用的终端网关之间移动或重新分配呼叫流量（基于其性能）来定期获得呼叫相关数据，分析数据，并适当地修改呼叫路由。

公开(公告)号：US5367206A

公开(公告)日：1994-11-22

申请号：US78711

申请日：1993-06-17

Applicant: James Yu ,  Tiao-Huo Kuo

Inventor： James Yu ,  Tiao-Huo Kuo

IPC: G11C17/00 ,  G11C16/06 ,  H03K17/16

CPC classification number: H03K17/164

Abstract: An output buffer circuit is disclosed that operates in low voltage applications but can be programmed using standard programmers at high voltage. The output buffer circuit provides for detecting a program verify logic signal from the programmer and slowing the output driver transistors when that signal is detected. In so doing, the noise problems associated with the higher voltages of programming a EPROM device are eliminated while at the same time allowing the output buffer circuit to operate at the required performance levels during normal operation.

Abstract translation: 公开了一种在低电压应用中工作的输出缓冲器电路，但可以使用高电压的标准编程器进行编程。 输出缓冲电路用于检测来自编程器的程序验证逻辑信号，并在检测到该信号时减慢输出驱动晶体管的输出。 在这样做时，消除了与EPROM器件编程的较高电压相关的噪声问题，同时允许输出缓冲器电路在正常操作期间以所需的性能水平运行。