公开(公告)号：US06207574B1

公开(公告)日：2001-03-27

申请号：US09353024

申请日：1999-07-13

申请人： Kang-Yoon Lee

发明人： Kang-Yoon Lee

IPC分类号： H01L21311

CPC分类号： H01L28/60 ,  H01L21/76895 ,  H01L28/84

摘要： A dynamic random access memory (DRAM) cell storage node and a fabricating method thereof are provided. A storage contact plug 118 is formed in a first insulating layer 104 on a semiconductor substrate. A second insulating layer 110, a material layer 112, and a third insulating layer 114 are sequentially formed on the first insulating layer. The material layer prevents etchant of the third insulating layer from attacking the second insulating layer. The third insulating layer, the material layer, and the second insulating layer are sequentially etched to form an opening exposing the storage contact plug and a portion of the surface of the first insulating layer. The opening is filled with a conductive layer to form a storage node 116. The third insulating layer is etched until the top surface of the material layer is exposed, and the material layer is etched until the top surface of the second insulating layer is exposed. Overetching is thus prevented, avoiding collapse or breakage of the storage node, dielectric leakage, and defective step coverage of upper electrodes.

摘要翻译： 提供了动态随机存取存储器（DRAM）单元存储节点及其制造方法。 存储接触插头118形成在半导体衬底上的第一绝缘层104中。 在第一绝缘层上依次形成第二绝缘层110，材料层112和第三绝缘层114。 材料层防止第三绝缘层的蚀刻剂侵蚀第二绝缘层。 依次蚀刻第三绝缘层，材料层和第二绝缘层，以形成露出存储接触插塞和第一绝缘层表面的一部分的开口。 开口填充有导电层以形成存储节点116.蚀刻第三绝缘层直到材料层的顶表面被暴露，并且材料层被蚀刻直到暴露第二绝缘层的顶表面。 因此防止了过蚀刻，避免了存储节点的塌陷或断裂，电介质泄漏和上部电极的阶跃覆盖不良。

公开(公告)号：US5795801A

公开(公告)日：1998-08-18

申请号：US694641

申请日：1996-08-09

申请人： Kang-yoon Lee

发明人： Kang-yoon Lee

IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L21/763 ,  H01L29/78 ,  H01L21/8238

CPC分类号： H01L21/763 ,  H01L21/76232 ,  H01L21/76237 ,  Y10S148/085 ,  Y10S148/086

摘要： A trench is formed in a substrate, the trench defining an active region surface on the substrate, the trench having a trench sidewall. A trench insulation region is then formed in the trench. The substrate underlying the trench sidewall is doped with impurities, and after the first doping, the substrate underlying the active region surface is doped with impurities to form a well having an impurity concentration which increases towards the trench sidewall in a predetermined manner. To form the trench, an insulation layer preferably is formed on the substrate, a barrier layer is formed on the insulation layer, and the barrier layer and the insulation layer are patterned to form an insulation region on the substrate and a barrier region on the insulation region. The substrate is then etched using the barrier region and the insulation region as a mask to thereby form a trench in the substrate. Preferably, the first doping includes implanting ions into the substrate through the trench insulation region and the trench sidewall using the barrier region as a mask. The second doping preferably is preceded by removal of the barrier region, and includes implanting ions into the substrate through the active region surface. The first implantation preferably occurs at a predetermined angle of incidence oblique to the active region surface or, more preferably, over a predetermined range of angles of incidence. The first and second doping steps may include doping with impurities of the same conductivity type or with opposite conductivity types.

摘要翻译： 在衬底中形成沟槽，沟槽在衬底上限定有源区表面，沟槽具有沟槽侧壁。 然后在沟槽中形成沟槽绝缘区域。 在沟槽侧壁下面的衬底掺杂有杂质，并且在第一掺杂之后，有源区表面下面的衬底掺杂杂质以形成具有以预定方式朝向沟槽侧壁增加的杂质浓度的阱。 为了形成沟槽，优选在衬底上形成绝缘层，在绝缘层上形成阻挡层，并对阻挡层和绝缘层进行图案化以在衬底上形成绝缘区域，并且在绝缘体上形成阻挡区域 地区。 然后使用阻挡区域和绝缘区域作为掩模蚀刻衬底，从而在衬底中形成沟槽。 优选地，第一掺杂包括通过沟槽绝缘区域和使用屏障区域作为掩模的沟槽侧壁将离子注入到衬底中。 优选在第二掺杂之前除去阻挡区，并且包括通过有源区表面将离子注入到衬底中。 第一植入优选地以与活性区域表面倾斜的预定入射角发生，或者更优选地在预定的入射角范围内发生。 第一和第二掺杂步骤可以包括掺杂相同导电类型或相反导电类型的杂质。