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    Method of fabricating semiconductor device with cell epitaxial layers partially overlap buried cell gate electrode
    2.
    发明授权
    Method of fabricating semiconductor device with cell epitaxial layers partially overlap buried cell gate electrode 有权
    制造具有电池外延层的半导体器件的方法部分地覆盖埋电池栅电极

    公开(公告)号：US08053307B2

    公开(公告)日：2011-11-08

    申请号：US12662393

    申请日：2010-04-14

    申请人： Hyeoung-Won Seo ,  Jae-Man Yoon ,  Kang-Yoon Lee ,  Bong-Soo Kim

    发明人： Hyeoung-Won Seo ,  Jae-Man Yoon ,  Kang-Yoon Lee ,  Bong-Soo Kim

    IPC分类号： H01L21/8234

    CPC分类号： H01L29/66628 ,  H01L27/10814 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/7834

    摘要： A semiconductor device may include a substrate having a cell active region. A cell gate electrode may be formed in the cell active region. A cell gate capping layer may be formed on the cell gate electrode. At least two cell epitaxial layers may be formed on the cell active region. One of the at least two cell epitaxial layers may extend to one end of the cell gate capping layer and another one of the at least two cell epitaxial layers may extend to an opposite end of the cell gate capping layer. Cell impurity regions may be disposed in the cell active region. The cell impurity regions may correspond to a respective one of the at least two cell epitaxial layers.

    摘要翻译： 半导体器件可以包括具有电池有源区的衬底。 可以在电池活性区域中形成电池栅电极。 单元栅极覆盖层可以形成在单元栅电极上。 至少两个电池外延层可以形成在电池有源区上。 至少两个单元外延层中的一个可以延伸到单元栅极覆盖层的一端，并且至少两个单元外延层中的另一个可以延伸到单元栅极覆盖层的相对端。 电池杂质区域可以设置在电池活性区域中。 电池杂质区域可以对应于至少两个电池外延层中的相应一个。

    SEMICONDUCTOR MEMORY DEVICE HAVING VERTICAL CHANNEL TRANSISTOR AND METHOD FOR FABRICATING THE SAME
    3.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE HAVING VERTICAL CHANNEL TRANSISTOR AND METHOD FOR FABRICATING THE SAME 有权
    具有垂直通道晶体管的半导体存储器件及其制造方法

    公开(公告)号：US20110186923A1

    公开(公告)日：2011-08-04

    申请号：US13085898

    申请日：2011-04-13

    申请人： Hyeoung-won Seo ,  Bong-soo Kim ,  Dong-gun Park ,  Kang-yoon Lee ,  Jae-man Yoon ,  Seong-goo Kim ,  Seung-bae Park

    发明人： Hyeoung-won Seo ,  Bong-soo Kim ,  Dong-gun Park ,  Kang-yoon Lee ,  Jae-man Yoon ,  Seong-goo Kim ,  Seung-bae Park

    IPC分类号： H01L29/78

    CPC分类号： H01L27/0207 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10888 ,  H01L27/10891

    摘要： Channels of two transistors are vertically formed on portions of two opposite side surfaces of one active region, and gate electrodes are vertically formed on a device isolation layer contacting the channels of the active region. A common bit line contact plug is formed in the central portions of the active region, two storage node contact plugs are formed on both sides of the bit line contact plug, and an insulating spacer is formed on a side surface of the bit line contact plug. A word line, a bit line, and a capacitor are sequentially stacked on the semiconductor substrate, like a conventional semiconductor memory device. Thus, effective space arrangement of a memory cell is possible such that a 4F2 structure is constituted, and a conventional line and contact forming process can be applied such that highly integrated semiconductor memory device is readily fabricated

    摘要翻译： 两个晶体管的沟道垂直地形成在一个有源区的两个相对的侧表面的部分上，并且栅极垂直地形成在与有源区的沟道接触的器件隔离层上。 在有源区域的中心部分形成共同的位线接触插塞，在位线接触插塞的两侧形成两个存储节点接触插塞，并且在位线接触插头的侧面上形成绝缘间隔件 。 像现有的半导体存储器件一样，在半导体衬底上顺序层叠字线，位线和电容器。 因此，存储单元的有效空间布置是可能的，使得构成4F2结构，并且可以应用常规的线和接触形成工艺，使得容易制造高度集成的半导体存储器件

    Integrated circuit package having an inductance loop formed from a multi-loop configuration
    5.
    发明授权
    Integrated circuit package having an inductance loop formed from a multi-loop configuration 有权
    具有由多回路配置形成的电感回路的集成电路封装

    公开(公告)号：US07768097B2

    公开(公告)日：2010-08-03

    申请号：US10927012

    申请日：2004-08-27

    申请人： Yido Koo ,  Hyungki Huh ,  Kang Yoon Lee ,  Jeong-Woo Lee ,  Joonbae Park ,  Kyeongho Lee

    发明人： Yido Koo ,  Hyungki Huh ,  Kang Yoon Lee ,  Jeong-Woo Lee ,  Joonbae Park ,  Kyeongho Lee

    IPC分类号： H01L23/58 ,  H01L29/00 ,  H03B7/06

    CPC分类号： H01L23/642 ,  H01L23/645 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05553 ,  H01L2224/48091 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01043 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2224/45099 ,  H01L2224/05599

    摘要： An integrated circuit package includes an inductance loop formed from a connection of lead wires and one or more input/output (I/O) package pins. In one embodiment, the inductance loop is formed from first and second wires which connect a first bonding pad on the integrated circuit chip to a first I/O pin of the package and a third and fourth wires which connect a second bonding pad on the chip to a second I/O pin of the package. To complete the inductor loop, the first and second I/O pins are connected by a third conductor between the pins. The third conductor may include one or more bonding wires and the I/O pins are preferably ones which are adjacent one another. However, the loop may be formed from non-adjacent connections of I/O pins based, for example, on loop-length requirements, space considerations, and/or other design or functional factors. In another embodiment, connection between the first and second I/O pins is established by making the I/O pins have a unitary construction. In another embodiment, connection between the first and second I/O pins is established by a metallization layer located either on the surface of the package substrate or within this substrate. By forming the inductor loop within the limits of the integrated circuit package, a substantial reduction in space requirements is realized, which, in turn, promotes miniaturization. Also, the integrated circuit may be implemented in any one of a variety of systems, at least one parameter of which is controlled by the length of the inductor loop of the package.

    摘要翻译： 集成电路封装包括由引线和一个或多个输入/输出（I / O）封装引脚的连接形成的电感回路。 在一个实施例中，电感回路由将集成电路芯片上的第一接合焊盘连接到封装的第一I / O引脚的第一和第二引线形成，以及连接芯片上的第二焊盘的第三和第四引线 到包的第二个I / O引脚。 为了完成电感线圈，第一和第二I / O引脚通过引脚之间的第三根导体连接。 第三导体可以包括一个或多个接合线，并且I / O引脚优选地彼此相邻。 然而，环路可以基于例如环路长度要求，空间考虑和/或其他设计或功能因素的I / O引脚的不相邻连接形成。 在另一个实施例中，通过使I / O引脚具有整体结构来建立第一和第二I / O引脚之间的连接。 在另一个实施例中，第一和第二I / O引脚之间的连接由位于封装基板的表面上或者在该基板内的金属化层建立。 通过在集成电路封装的极限内形成电感器回路，实现了空间要求的显着降低，这反过来促进了小型化。 此外，集成电路可以在各种系统中的任何一个中实现，其中的至少一个参数由封装的电感器环的长度来控制。

    DRAM device with cell epitaxial layers partially overlap buried cell gate electrode
    7.
    发明授权
    DRAM device with cell epitaxial layers partially overlap buried cell gate electrode 有权
    具有电池外延层的DRAM器件部分地覆盖埋电池栅电极

    公开(公告)号：US07728373B2

    公开(公告)日：2010-06-01

    申请号：US11705109

    申请日：2007-02-12

    申请人： Hyeoung-Won Seo ,  Jae-Man Yoon ,  Kang-Yoon Lee ,  Bong-Soo Kim

    发明人： Hyeoung-Won Seo ,  Jae-Man Yoon ,  Kang-Yoon Lee ,  Bong-Soo Kim

    IPC分类号： H01L21/2842

    CPC分类号： H01L29/66628 ,  H01L27/10814 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/7834

    摘要： A semiconductor device may include a substrate having a cell active region. A cell gate electrode may be formed in the cell active region. A cell gate capping layer may be formed on the cell gate electrode. At least two cell epitaxial layers may be formed on the cell active region. One of the at least two cell epitaxial layers may extend to one end of the cell gate capping layer and another one of the at least two cell epitaxial layers may extend to an opposite end of the cell gate capping layer. Cell impurity regions may be disposed in the cell active region. The cell impurity regions may correspond to a respective one of the at least two cell epitaxial layers.

    摘要翻译： 半导体器件可以包括具有电池有源区的衬底。 可以在电池活性区域中形成电池栅电极。 单元栅极覆盖层可以形成在单元栅电极上。 至少两个电池外延层可以形成在电池有源区上。 至少两个单元外延层中的一个可以延伸到单元栅极覆盖层的一端，并且至少两个单元外延层中的另一个可以延伸到单元栅极覆盖层的相对端。 电池杂质区域可以设置在电池活性区域中。 电池杂质区域可以对应于至少两个电池外延层中的相应一个。

    Semiconductor device having storage nodes and its method of fabrication
    8.
    发明授权
    Semiconductor device having storage nodes and its method of fabrication 失效
    具有存储节点的半导体器件及其制造方法

    公开(公告)号：US07691719B2

    公开(公告)日：2010-04-06

    申请号：US11457726

    申请日：2006-07-14

    申请人： Cheol-Ju Yun ,  Kang-Yoon Lee ,  In-Ho Nam

    发明人： Cheol-Ju Yun ,  Kang-Yoon Lee ,  In-Ho Nam

    IPC分类号： H01L21/20 ,  H01L21/8242

    CPC分类号： H01L21/76885 ,  H01L21/76834 ,  H01L27/10855

    摘要： Embodiments of a semiconductor device having storage nodes include an interlayer insulating layer disposed on a semiconductor substrate; a conductive pad disposed in the interlayer insulating layer to contact with a predetermined portion of the substrate, an upper portion of the conductive pad protruding above the interlayer insulating layer; an etch stop layer disposed on the conductive pad and the interlayer insulating layer; and storage nodes penetrating the etch stop layer and disposed on the conductive pad. A penetration path of wet etchant is completely blocked during the wet etch process that removes the mold oxide layer. Therefore, inadvertent etching of the insulating layer due to penetration of wet etchant is prevented, resulting in a stronger, more stable, storage node structure.

    摘要翻译： 具有存储节点的半导体器件的实施例包括设置在半导体衬底上的层间绝缘层; 布置在所述层间绝缘层中以与所述基板的预定部分接触的导电焊盘，所述导电焊盘的上部突出于所述层间绝缘层的上方; 设置在所述导电焊盘和所述层间绝缘层上的蚀刻停止层; 并且存储节点穿透蚀刻停止层并且设置在导电焊盘上。 在湿法蚀刻工艺期间，湿蚀刻剂的穿透路径被完全阻挡，从而去除了模具氧化物层。 因此，防止了由于潮湿蚀刻剂的渗透而导致的绝缘层的无意蚀刻，导致更坚固，更稳定的存储节点结构。

    HIGH RESOLUTION TIME DETECTING APPARATUS USING INTERPOLATION AND TIME DETECTING METHOD USING THE SAME
    10.
    发明申请
    HIGH RESOLUTION TIME DETECTING APPARATUS USING INTERPOLATION AND TIME DETECTING METHOD USING THE SAME 有权
    使用插值和时间检测方法的高分辨率时间检测装置

    公开(公告)号：US20090027088A1

    公开(公告)日：2009-01-29

    申请号：US11935424

    申请日：2007-11-06

    申请人： Tae-wook KIM ,  Choong-yul CHA ,  Jae-sup LEE ,  Kang-yoon LEE

    发明人： Tae-wook KIM ,  Choong-yul CHA ,  Jae-sup LEE ,  Kang-yoon LEE

    IPC分类号： H03B21/00

    CPC分类号： H03D13/00 ,  H03L7/091 ,  H03L2207/50

    摘要： A high resolution time detecting apparatus using interpolation and a time detecting method using the same are provided. The time detecting apparatus includes a delayer which generates delayed signals by sequentially delaying a reference signal using a plurality of delay elements, a latch unit which outputs latch signals using the delayed signals, and an interpolation unit which outputs interpolated signals using input and output signals of the delay elements. As a result, a high resolution TDC using an interpolation and a time detecting method using the same provide improved performance of digital PLL, high resolution digital signal output at a low power consumption, and controlled circuit size.

    摘要翻译： 提供了使用内插的高分辨率时间检测装置和使用其的时间检测方法。 时间检测装置包括：延迟器，其通过使用多个延迟元件顺序延迟参考信号来产生延迟信号;锁存单元，其使用延迟信号输出锁存信号;以及内插单元，其使用输入和输出信号输出内插信号 延迟元素。 结果，使用内插的高分辨率TDC和使用其的时间检测方法提供了数字PLL，低功耗的高分辨率数字信号输出和受控电路尺寸的改进的性能。