公开(公告)号：US08803556B1

公开(公告)日：2014-08-12

申请号：US13669265

申请日：2012-11-05

Applicant: Marvell Israel (M.I.S.L.) Ltd.

Inventor： Shimon Avitan

IPC: H03K5/22

CPC classification number: H03K5/26

Abstract: Some of the embodiments of the present disclosure provide a method comprising receiving a first signal and a second signal; generating a first digital count corresponding to a characteristic of the first signal; subsequent to generating the first digital count, generating a second digital count corresponding to a characteristic of the second signal; and comparing the first digital count with the second digital count. Other embodiments are also described and claimed.

Abstract translation: 本公开的一些实施例提供了一种方法，包括接收第一信号和第二信号; 产生对应于第一信号的特性的第一数字计数; 在产生所述第一数字计数之后，产生对应于所述第二信号的特性的第二数字计数; 以及将所述第一数字计数与所述第二数字计数进行比较。 还描述和要求保护其他实施例。

公开(公告)号：US20140169382A1

公开(公告)日：2014-06-19

申请号：US14188484

申请日：2014-02-24

Applicant: MARVELL INTERNATIONAL LTD. ,  MARVELL ISRAEL (M.I.S.L) LTD.

Inventor： David Melman ,  Nir Arad ,  Nafea Bishara

IPC: H04L12/715 ,  H04L12/751 ,  H04L12/46

CPC classification number: H04L45/04 ,  H04L12/46 ,  H04L12/4625 ,  H04L45/00 ,  H04L45/08 ,  H04L45/60 ,  H04L49/109 ,  H04L49/351

Abstract: A network device includes a plurality of physical ports configured to be coupled to one or more networks, and a processor device configured to process packets. The processor device includes a processor configured to implement a logical port assignment mechanism to assign source logical port information to a data packet received via a source physical port of the plurality of physical ports. The source logical port information is assigned based on one or more characteristics of the data packet, and the source logical port information corresponds to a logical entity that is different from any physical port. The processor device also includes a forwarding engine processor configured to determine one or more egress logical ports for forwarding the data packet, map the egress logical port(s) to respective egress physical port(s) of the plurality of physical ports, and forward the data packet to the egress physical port(s) based on the mapping.

Abstract translation: 网络设备包括被配置为耦合到一个或多个网络的多个物理端口，以及被配置为处理分组的处理器设备。 处理器设备包括处理器，其被配置为实现逻辑端口分配机制，以将源逻辑端口信息分配给经由多个物理端口的源物理端口接收的数据包。 根据数据包的一个或多个特性分配源逻辑端口信息，源逻辑端口信息对应于与任何物理端口不同的逻辑实体。 处理器设备还包括转发引擎处理器，其被配置为确定用于转发数据分组的一个或多个出口逻辑端口，将出口逻辑端口映射到多个物理端口的相应出口物理端口，并且转发 基于映射的到出口物理端口的数据分组。

公开(公告)号：US08743882B1

公开(公告)日：2014-06-03

申请号：US13863858

申请日：2013-04-16

Applicant: Marvell Israel (M.I.S.L) Ltd.

Inventor： Yaniv Kopelman ,  Nafea Bishara ,  Yariv Anafi

IPC: H04L12/28 ,  H04L29/06 ,  H04L12/56 ,  H04L12/54

CPC classification number: H04L61/103 ,  H04L12/462 ,  H04L29/0602 ,  H04L69/22

Abstract: A packet processor for a network device includes an incoming port that receives a first packet. The first packet includes a data portion, a control portion and a first outgoing port. A control data processing device receives the control portion from the incoming port while the data portion is stored in memory, and transmits the control portion to the first outgoing port. The first outgoing port transmits a first request for the data portion based on the control portion. A header altering device retrieves the data portion from the memory and strips, modifies, and encapsulates the data portion based on the first request.

Abstract translation: 用于网络设备的分组处理器包括接收第一分组的输入端口。 第一分组包括数据部分，控制部分和第一输出端口。 控制数据处理装置在将数据部分存储在存储器中的同时从输入端口接收控制部分，并将控制部分发送到第一输出端口。 第一输出端口基于控制部分发送对数据部分的第一请求。 报头更换设备从存储器检索数据部分，并根据第一请求剥离，修改和封装数据部分。

公开(公告)号：US08729942B2

公开(公告)日：2014-05-20

申请号：US14085475

申请日：2013-11-20

Applicant: Marvell Israel (M.I.S.L) Ltd.

Inventor： Mel Bazes

IPC: H03K3/00

CPC classification number: H03K3/00 ,  H03K3/0375 ,  H03K3/356173

Abstract: Some of the embodiments of the present disclosure provide a D-type flip-flop, comprising a first latch configured to generate a sample enable signal, based on logical states of an input signal, and generate a sampled signal, based on logical states of the input signal and the sample enable signal; and a second latch configured to generate an output signal responsively to the sampled signal. Other embodiments are also described and claimed.

Abstract translation: 本公开的一些实施例提供了一种D型触发器，包括：第一锁存器，被配置为基于输入信号的逻辑状态产生采样使能信号，并且基于所述第一锁存器的逻辑状态生成采样信号 输入信号和采样使能信号; 以及第二锁存器，被配置为响应于采样信号产生输出信号。 还描述和要求保护其他实施例。

公开(公告)号：US08700869B1

公开(公告)日：2014-04-15

申请号：US13863088

申请日：2013-04-15

Applicant: Marvell Israel (M.I.S.L) Ltd.

Inventor： Eitan Rosen

IPC: G06F12/00

CPC classification number: G06F9/3851 ,  G06F9/30123 ,  G06F9/30141

Abstract: A multithreading memory system, and a processor that incorporates a multithreading memory system, includes a main memory element, plural auxiliary memory elements, and a selector. The main memory element may be configured to receive a data signal and a select signal. The auxiliary memory elements may be configured to receive an output signal from the main memory element. The selector may be configured to receive an output signal from one of the auxiliary memory elements and a scan input signal. The selector may select the output signal from the auxiliary memory element or the scan input signal based on an advance thread signal. The selected one of the output signal from the at least one special memory element and the scan input signal may be forwarded to the main memory element as the control signal.

Abstract translation: 多线程存储器系统和包含多线程存储器系统的处理器包括主存储器元件，多个辅助存储器元件和选择器。 主存储元件可以被配置为接收数据信号和选择信号。 辅助存储器元件可以被配置为从主存储器元件接收输出信号。 选择器可以被配置为从辅助存储器元件之一接收输出信号和扫描输入信号。 选择器可以基于提前线程信号从辅助存储器元件或扫描输入信号中选择输出信号。 来自至少一个特殊存储元件的输出信号和扫描输入信号中所选择的一个可以作为控制信号被转发到主存储元件。

公开(公告)号：US08471215B1

公开(公告)日：2013-06-25

申请号：US13707117

申请日：2012-12-06

Applicant: Marvell Israel (M.I.S.L) Ltd.

Inventor： Eli Kurin ,  Ran Manor ,  Gil Weisman ,  Yair Faiershtein

IPC: G01T1/00

CPC classification number: G01R31/31816 ,  G01N2223/6113 ,  G01N2223/626

Abstract: Test samples for use in conducting integrated circuit alpha particle emissions testing, processes for preparing test samples for use in conducting integrated circuit alpha particle emissions testing, and processes for conducting integrated circuit alpha particle emissions testing using the test samples, are described. The approach takes into account the effects of the relative physical positions of the respective components within a final integrated circuit package, and takes into account the effect of contamination of individual components or of the integrated circuit package as a whole due to conditions and/or processes performed during the production process. The described approach relates to test sample preparation and integrated circuit alpha particle emissions testing for integrated circuits in which the alpha particle emission levels are extremely low, i.e., in the ultra low alpha region, for example, alpha particle emissions less than 0.002 cph/cm2.

Abstract translation: 描述了用于进行集成电路α粒子排放测试的测试样品，用于制备用于进行集成电路α粒子排放测试的测试样品的过程，以及使用测试样品进行集成电路α粒子排放测试的过程。 该方法考虑了最终集成电路封装内的相应部件的相对物理位置的影响，并考虑到由于条件和/或过程而导致的单个部件或集成电路封装的整体污染的影响 在生产过程中执行。 所描述的方法涉及用于集成电路的测试样品制备和集成电路α粒子排放测试，其中α粒子发射水平极低，即在超低α区域，例如，小于0.002cph / cm 2的α粒子发射 。

公开(公告)号：US12238001B1

公开(公告)日：2025-02-25

申请号：US17744493

申请日：2022-05-13

Applicant: Marvell Israel (M.I.S.L) Ltd.

Inventor： Jacob Jul Schroder ,  Itay Shlomo Peled

IPC: H04L12/66 ,  H04L45/74 ,  H04L47/32

Abstract: A network device comprises a receive processor configured to generate respective packet descriptors that include i) respective header information extracted from headers of packets received via a plurality of network interfaces, the packets also including trailers, and ii) respective trailer information extracted from the trailers of the packets. A packet processor is configured to process the header information and the trailer information in the packet descriptors to determine actions to be performed on the packets, including determining network interfaces via which at least some packets are to be transmitted by the network device. A transmit processor is configured to transmit the at least some packets via the plurality of network interfaces in accordance with the determining of network interfaces by the packet processor.

公开(公告)号：US20240430030A1

公开(公告)日：2024-12-26

申请号：US18815655

申请日：2024-08-26

Applicant: Marvell Israel (M.I.S.L) Ltd.

Inventor： Nitzan DROR ,  Joergen P.R. Hofman-Bang

IPC: H04J3/06

Abstract: A processor of a network device determines a timestamping method for communicating timing information corresponding to transmission of a timing message to another network device. The timestamping method is selected from a set of multiple timestamping methods that the network device is configured to perform, including: i) a one-step timestamping method, and ii) a two-step timestamping method. The processor generates a control header corresponding to the timing message, which includes a first field and a second field, the second field indicating a type of information within the first field. The first field indicates the timestamping method. The processor transfers the timing message to timestamping circuitry; and transfers the control header to the timestamping circuitry to indicate to the timestamping circuitry the timestamping method to be performed by the timestamping circuitry in connection with transmitting the timing message to the other network device.

公开(公告)号：US12107671B2

公开(公告)日：2024-10-01

申请号：US18114171

申请日：2023-02-24

Applicant: Marvell Israel (M.I.S.L) Ltd.

Inventor： Nitzan Dror ,  Jeng-Jong Douglas Chen ,  Lenin Kumar Patra

IPC: H04J3/06

CPC classification number: H04J3/0661 ,  H04J3/0682

Abstract: Timestamp circuitry of a network device modifies a packet by embedding a future timestamp in the packet to generate a timestamped packet. The future timestamp corresponds to a transmit time that occurs after the timestamp circuitry embeds the future timestamp in the packet. The timing information is added to the packet and the packet is then transferred to transmitter circuitry of the network device via a communication link, internal to the network device, that operates according to a media independent communication interface. Time gating circuitry of the transmitter circuitry i) holds the timestamped packet from proceeding to a network link coupled to the network device prior to a current time reaching the transmit time, and ii) releases the timestamped packet for transmission via the network link in response to the current time reaching the transmit time.

公开(公告)号：US12088562B1

公开(公告)日：2024-09-10

申请号：US17860414

申请日：2022-07-08

Applicant: Marvell Israel (M.I.S.L) Ltd.

Inventor： Ayal Lior ,  Joergen P. R. Hofman-Bang ,  Itay Shlomo Peled

IPC: H04L9/40 ,  H04L12/46 ,  H04L9/32 ,  H04W12/06

CPC classification number: H04L63/029 ,  H04L12/4633 ,  H04L63/0428 ,  H04L9/3242 ,  H04L63/0485 ,  H04W12/06

Abstract: A network device is capable of transmitting and/or receiving packets that are encrypted according to a particular network security protocol, while being encapsulated according to any of a variety of tunneling protocols independent of the particular network security protocol. In such embodiments, a customer or network administrator can use the particular network security protocol while having the freedom to choose a particular tunneling protocol that is best suited for a network implementation instead of being limited to a specific tunneling protocol for a particular network security protocol.