HIGH MOBILITY TFT DRIVING DEVICE AND MANUFACTURING METHOD THEREOF

    公开(公告)号:US20240405083A1

    公开(公告)日:2024-12-05

    申请号:US18696151

    申请日:2023-06-08

    Abstract: The present invention relates to a high-mobility driving element and a method for manufacturing same, the high-mobility driving element comprising: a substrate; an insulating film disposed on the substrate; a channel layer disposed on at least a partial region of the insulating film and including a metal oxide; a source electrode and a drain electrode connected to the channel layer and disposed on the insulating film and either side of the channel layer to face each other; and a protective layer covering all of the channel layer, the source electrode, and the drain electrode, wherein the channel layer comprises a plurality of fluorinated regions in at least a partial region between the source electrode and the drain electrode.

    CAPACITORLESS 3D STACKED DRAM DEVICE AND MANUFACTURING METHOD THEREOF

    公开(公告)号:US20240397699A1

    公开(公告)日:2024-11-28

    申请号:US18570810

    申请日:2023-10-17

    Abstract: The present disclosure discloses a capacitorless three-dimensional stacked DRAM device including a plurality of memory cell structures spaced apart from each other in horizontal and vertical directions, each of the plurality of memory cell structures including a horizontal read transistor structure and a horizontal write transistor structure, a plurality of write bit lines connected to the plurality of write transistor structures of the plurality of memory cell structures and extending in the horizontal direction, a plurality of read bit lines connected to the plurality of read transistor structures of the plurality of memory cell structures and extending in the horizontal direction, a plurality of write word lines connected to the plurality of write transistor structures and extending in the vertical direction, and a plurality of read word lines connected to the plurality of read transistor structures and extending in the vertical direction.

    ARTIFICIAL NEURAL NETWORK CALCULATION METHOD AND DEVICE BASED ON PARAMETER QUANTIZATION USING HYSTERESIS

    公开(公告)号:US20240394534A1

    公开(公告)日:2024-11-28

    申请号:US18795315

    申请日:2024-08-06

    Abstract: Artificial neural network calculation method and device based on parameter quantization using hysteresis are proposed to reduce a size of an artificial neural network. The artificial neural network calculation method may comprise: determining a parameter gradient of a parameter based on a first quantization parameter value of the parameter of the artificial neural network; determining a second original parameter value of the parameter based on a first original parameter value associated with the parameter gradient and the first quantization parameter value; and determining a second quantization parameter value associated with the second original parameter value based on a result of comparing the first quantization parameter value with the second original parameter value. By applying hysteresis to parameter quantization, variability may be reduced, each parameter may be trained more stably, and the performance of a quantized model is improved.

    CIRCUIT DESIGN METHOD AND APPARATUS

    公开(公告)号:US20240394449A1

    公开(公告)日:2024-11-28

    申请号:US18795368

    申请日:2024-08-06

    Abstract: Proposed is a circuit design method and device that automatically designs circuits by generating candidate circuit structures and optimizing transistor sizes. According to the circuit design method and device, design time and cost are reduced, and circuit performance is improved. The circuit design method may comprise: generating, by a processor, a candidate circuit structure by executing a genetic algorithm based on a gene and associated with a circuit topology graph; and optimizing, by the processor, a transistor size of the candidate circuit structure by executing a reinforcement learning algorithm based on analysis of multiple process corners.

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