公开(公告)号：US07627076B2

公开(公告)日：2009-12-01

申请号：US11676866

申请日：2007-02-20

申请人： Youichi Tobita

发明人： Youichi Tobita

IPC分类号： G11C19/00

CPC分类号： G11C19/28 ,  G11C19/184

摘要： In a shift register circuit, a reduction of a driving capability caused by an increased operating rate is prevented. A shift register circuit includes a first transistor between an output terminal and a clock terminal, a second transistor between the output terminal and a first power-supply terminal, and a third transistor between the gate of the first transistor and a second power-supply terminal. The shift register circuit further includes a fourth transistor that charges the gate node of the third transistor on the basis of a signal inputted to a first input terminal, and a capacitive element that boosts the gate node of the third transistor that has been charged.

摘要翻译： 在移位寄存器电路中，防止了由增加的工作速率引起的驱动能力的降低。 移位寄存器电路包括在输出端子和时钟端子之间的第一晶体管，在输出端子和第一电源端子之间的第二晶体管，以及在第一晶体管的栅极和第二电源端子之间的第三晶体管 。 移位寄存器电路还包括基于输入到第一输入端子的信号对第三晶体管的栅极节点进行充电的第四晶体管，以及对已经被充电的第三晶体管的栅极节点进行升压的电容元件。

公开(公告)号：US07504869B2

公开(公告)日：2009-03-17

申请号：US11265076

申请日：2005-11-03

申请人： Youichi Tobita ,  Seiichirou Mori ,  Hiroyuki Murai

发明人： Youichi Tobita ,  Seiichirou Mori ,  Hiroyuki Murai

IPC分类号： H03K21/00

CPC分类号： H02M3/07 ,  G09G3/3696 ,  G09G2330/028 ,  H03B19/14

摘要： A level shifter and a charge pump circuit are added, among cascade-connected unit frequency dividing circuits forming a frequency dividing circuit, to the unit frequency dividing circuit in the first stage. The charge pump circuit boosts an input voltage based on a dot clock signal, and supplies the booster voltage to the unit frequency dividing circuit in the first stage. The unit frequency dividing circuit in the first stage, which is driven by the booster voltage, attains an improved current driving capability. The improved current driving capability of the unit frequency dividing circuit in the first stage to which the dot clock signal of high frequency is input leads to a widened operating margin of the frequency dividing circuit.

摘要翻译： 在形成分频电路的级联连接单元分频电路中，将电平移位器和电荷泵电路加到第一级中的单位分频电路。 电荷泵电路基于点时钟信号来提高输入电压，并将升压电压提供给第一级中的单位分频电路。 由升压电压驱动的第一级中的单位分频电路获得改善的电流驱动能力。 在输入高频点时钟信号的第一级中的单位分频电路的改进的电流驱动能力导致分频电路加宽的工作裕度。

公开(公告)号：US20080187089A1

公开(公告)日：2008-08-07

申请号：US11968470

申请日：2008-01-02

申请人： Takashi Miyayama ,  Youichi Tobita ,  Hiroyuki Murai ,  Seiichiro Mori

发明人： Takashi Miyayama ,  Youichi Tobita ,  Hiroyuki Murai ,  Seiichiro Mori

IPC分类号： G11C19/00 ,  H03L5/00

CPC分类号： G11C19/28

摘要： A dual-gate transistor formed of two transistors connected in series between a first power terminal and a first node is used as a charging circuit for charging a gate node (first node) of a transistor intended to pull up an output terminal of a unit shift register. The dual-gate transistor is configured such that the connection node (second node) between the two transistors constituting the dual-gate transistor is pulled down to the L level by the capacitive coupling between the gate and second node in accordance with the change of the gate from the H level to the L level.

摘要翻译： 由串联在第一电源端子和第一节点之间的两个晶体管形成的双栅极晶体管用作充电电路，用于对旨在上拉单元偏移的输出端子的晶体管的栅极节点（第一节点）充电 寄存器。 双栅极晶体管被配置为使得构成双栅极晶体管的两个晶体管之间的连接节点（第二节点）根据栅极和第二节点的变化被下拉到L电平 门从H级到L级。

公开(公告)号：US07362318B2

公开(公告)日：2008-04-22

申请号：US10899000

申请日：2004-07-27

申请人： Youichi Tobita

发明人： Youichi Tobita

IPC分类号： G09G5/00 ,  G09G5/10

CPC分类号： G09G3/3688 ,  G09G3/3208 ,  G09G2310/027 ,  H01L27/1214 ,  H01L27/1255 ,  H01L27/127 ,  H03M1/76

摘要： The decode circuit includes decode paths corresponding to gray-scale voltages. Each decode path has decode transistors connected serially and corresponding to display signal bits. In a selected decode path, the decode transistors connected serially are all turned on to transmit the corresponding gray-scale voltage to output node of the decode circuit. The gate of each of the decode transistors is connected to one signal line of first and second signal lines transmitting the corresponding display signal bits and inverted signals of the corresponding display signal bits, respectively. The other signal line not connected to the gate is disposed so as to create a parasitic capacitance similar to a gate capacitance between a node connected to the source or drain of the decode transistor and the other signal line. Accordingly, noise resistance in the decode circuit for gray-scale expression can be enhanced with suppressing increase in circuit area.

摘要翻译： 解码电路包括对应于灰度级电压的解码路径。 每个解码路径具有串行连接并对应于显示信号位的解码晶体管。 在选择的解码路径中，串行连接的解码晶体全部导通，将相应的灰度电压发送到解码电路的输出节点。 每个解码晶体管的栅极分别连接到发送对应的显示信号位的相应显示信号位和反相信号的第一和第二信号线的一条信号线。 未连接到栅极的另一信号线设置成产生类似于连接到解码晶体管的源极或漏极的节点与另一个信号线之间的栅极电容的寄生电容。 因此，通过抑制电路面积的增加，可以提高用于灰度表达的解码电路中的噪声电阻。

公开(公告)号：US20080080661A1

公开(公告)日：2008-04-03

申请号：US11856264

申请日：2007-09-17

申请人： Youichi TOBITA

发明人： Youichi TOBITA

IPC分类号： G11C19/28

CPC分类号： G11C19/28

摘要： A high-speed shift register circuit is provided. The shift register circuit includes a first transistor supplying a clock signal to a first output terminal, a second transistor discharging the first output terminal, a third transistor supplying the above clock signal to a second output terminal, and a fourth transistor discharging the second output terminal. The gates of the first and third transistors are both connected to a first node, and the gates of the second and fourth transistors are both connected to a second node. The first node is charged by a fifth transistor which is connected between the first node and a first input terminal and which has a gate connected to a second input end.

摘要翻译： 提供高速移位寄存器电路。 移位寄存器电路包括向第一输出端子提供时钟信号的第一晶体管，对第一输出端子放电的第二晶体管，向第二输出端子提供上述时钟信号的第三晶体管，以及将第二输出端子 。 第一和第三晶体管的栅极都连接到第一节点，并且第二和第四晶体管的栅极都连接到第二节点。 第一节点被第五晶体管充电，第五晶体管连接在第一节点和第一输入端之间，并且具有连接到第二输入端的栅极。

公开(公告)号：US07324079B2

公开(公告)日：2008-01-29

申请号：US10494280

申请日：2002-11-20

申请人： Youichi Tobita

发明人： Youichi Tobita

IPC分类号： G09G3/36

CPC分类号： G09G3/20 ,  G09G3/3233 ,  G09G3/3291 ,  G09G3/3688 ,  G09G3/3696 ,  G09G2310/0248 ,  G09G2310/0297 ,  G09G2330/021 ,  G09G2330/028

摘要： A gradation potential generating circuit in a color liquid crystal display device includes 65 resistance elements connected in series and dividing a voltage applied between first and second nodes to generate 64 gradation potentials; a first current amplifier circuit provided corresponding to each gradation potential higher than a precharge potential of a data line and having charging capability higher than discharging capability; and a second current amplifier circuit provided corresponding to each gradation potential lower than the precharge potential and having discharging capability higher than charging capability.

摘要翻译： 彩色液晶显示装置中的灰度势产生电路包括串联连接的65个电阻元件，并分割施加在第一和第二节点之间的电压以产生64个灰度电位; 对应于高于数据线的预充电电位且具有高于放电能力的充电能力的每个灰度级电位设置的第一电流放大器电路; 以及第二电流放大器电路，其对应于低于预充电电位并且具有高于充电能力的放电能力的每个灰度级电位。

公开(公告)号：US20070216626A1

公开(公告)日：2007-09-20

申请号：US11802446

申请日：2007-05-23

申请人： Youichi Tobita ,  Yuzo Odoi

发明人： Youichi Tobita ,  Yuzo Odoi

IPC分类号： G09G3/36

CPC分类号： H03M1/82 ,  G09G3/3233 ,  G09G3/3291 ,  G09G3/3688 ,  G09G2300/0842 ,  G09G2310/0248 ,  G09G2310/027 ,  G09G2320/041

摘要： A pulse number control circuit inputs, to a charge pump circuit, pulses of a number according to digital data constituted of weighted data bits. The charge pump circuit includes a pump capacitor connected between a first node to which the pulses are input and a second node, a switch element connected between the second node and an output node, and a bias circuit. According to a change of a voltage on the output node, the bias circuit changes a voltage on the second node with the same polarity.

公开(公告)号：US07236152B2

公开(公告)日：2007-06-26

申请号：US10802771

申请日：2004-03-18

申请人： Youichi Tobita ,  Yuzo Odoi

发明人： Youichi Tobita ,  Yuzo Odoi

IPC分类号： G09G3/36

CPC分类号： H03M1/82 ,  G09G3/3233 ,  G09G3/3291 ,  G09G3/3688 ,  G09G2300/0842 ,  G09G2310/0248 ,  G09G2310/027 ,  G09G2320/041

摘要： A pulse number control circuit inputs, to a charge pump circuit, pulses of a number according to digital data constituted of weighted data bits. The charge pump circuit includes a pump capacitor connected between a first node to which the pulses are input and a second node, a switch element connected between the second node and an output node, and a bias circuit. According to a change of a voltage on the output node, the bias circuit changes a voltage on the second node with the same polarity.

摘要翻译： 脉冲数控制电路根据由加权数据位构成的数字数据向电荷泵电路输入一个数量的脉冲。 电荷泵电路包括连接在输入脉冲的第一节点和第二节点之间的泵电容器，连接在第二节点和输出节点之间的开关元件以及偏置电路。 根据输出节点上的电压的变化，偏置电路以相同的极性改变第二节点上的电压。

公开(公告)号：US20070057897A1

公开(公告)日：2007-03-15

申请号：US11593095

申请日：2006-11-06

申请人： Youichi Tobita

发明人： Youichi Tobita

IPC分类号： G09G3/36

CPC分类号： G09G3/20 ,  G09G3/3233 ,  G09G3/3291 ,  G09G3/3688 ,  G09G3/3696 ,  G09G2310/0248 ,  G09G2310/0297 ,  G09G2330/021 ,  G09G2330/028

摘要： A gradation potential generating circuit (24) in a color liquid crystal display device includes 65 resistance elements connected in series and dividing a voltage applied between first and second nodes to generate 64 gradation potentials; a first current amplifier circuit provided corresponding to each gradation potential higher than a precharge potential of a data line and having charging capability higher than discharging capability; and a second current amplifier circuit provided corresponding to each gradation potential lower than the precharge potential and having discharging capability higher than charging capability.

摘要翻译： 彩色液晶显示装置中的灰度势产生电路（24）包括串联连接的65个电阻元件，并分割施加在第一和第二节点之间的电压以产生64个灰度电位; 对应于高于数据线的预充电电位且具有高于放电能力的充电能力的每个灰度级电位设置的第一电流放大器电路; 以及第二电流放大器电路，其对应于低于预充电电位并且具有高于充电能力的放电能力的每个灰度级电位。

公开(公告)号：US07187373B2

公开(公告)日：2007-03-06

申请号：US10492046

申请日：2002-10-11

申请人： Youichi Tobita

发明人： Youichi Tobita

IPC分类号： G09G5/00

CPC分类号： G09G3/3688 ,  G02F1/136213 ,  G09G3/006 ,  G09G3/3648 ,  G09G2300/0842 ,  G09G2310/0248

摘要： Amplifier circuits (AMPi, AMPj) are provided corresponding to data lines (DLi, DLj) arranged corresponding to columns of display pixels (PX). In the amplifier circuit, a non-inversion input of a differential amplifier circuit (32) is connected to the corresponding data line, and an inversion input node (N2) is connected to a capacitance element (34). Before pixel data of a displaying pixel element is read onto the data line, the non-inversion input of the differential amplifier circuit is precharged to a predetermined voltage level, and an output node of the differential amplifier circuit is coupled to the inversion input node (N2). The differential amplifier circuit operates as a voltage follower, and the capacitance element stores a comparison reference voltage including information corresponding to an offset of the differential amplifier circuit. Thereafter, data of the displaying pixel element is read onto the data line, and is amplified by the amplifier circuit so that the pixel data can be accurately amplified while canceling the offset of the differential amplifier circuit.

摘要翻译： 对应于对应于显示像素列（PX）排列的数据线（DLi，DLj）提供放大器电路（AMPi，AMPj）。 在放大器电路中，差分放大电路（32）的非反相输入端连接到对应的数据线，反相输入节点（N 2）连接到电容元件（34）。 在显示像素元素的像素数据被读取到数据线之前，差分放大器电路的非反相输入被预充电到预定电压电平，并且差分放大器电路的输出节点耦合到反相输入节点 N 2）。 差分放大器电路作为电压跟随器工作，并且电容元件存储包括与差分放大器电路的偏移相对应的信息的比较参考电压。 此后，显示像素元素的数据被读取到数据线上，并被放大电路放大，使得可以在消除差分放大器电路的偏移的同时精确地放大像素数据。