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71.发明授权Method and system for dynamically configuring a central processing unit with multiple processing cores 有权用于动态配置具有多个处理核心的中央处理单元的方法和系统公开(公告)号：US06550020B1
公开(公告)日：2003-04-15
申请号：US09483260
申请日：2000-01-10
IPC分类号： G06F1100
CPC分类号： G06F11/2028 , G06F11/1417 , G06F11/2035
摘要： A data processing system has at least one integrated circuit containing a central processing unit (CPU) that includes at least first and second processing cores. The integrated circuit also includes input facilities that receive control input specifying which of the processing cores is to be utilized. In addition, the integrated circuit includes configuration logic that decodes the control input and, in response, selectively controls reception of input signals and transmission of output signals of one or more of the processing cores in accordance with the control input. In an illustrative embodiment, the configuration logic is partial-good logic that configures the integrated circuit to utilize the second processing core, in lieu of a defective or inactive first processing core, as a virtual first processing core.
摘要翻译： 数据处理系统具有至少一个包含至少包括第一和第二处理核心的中央处理单元（CPU）的集成电路。 该集成电路还包括接收控制输入的输入设备，该控制输入指定要使用哪个处理核心。 此外，集成电路包括对控制输入进行解码的配置逻辑，并且作为响应，根据控制输入选择性地控制输入信号的接收和一个或多个处理核的输出信号的传输。 在说明性实施例中，配置逻辑是部分良好的逻辑，其将集成电路配置为利用第二处理核，以代替有缺陷或不活动的第一处理核作为虚拟第一处理核。
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公开(公告)号：US06438722B1
公开(公告)日：2002-08-20
申请号：US09372697
申请日：1999-08-11
申请人： Roger Ned Bailey , Michael Stephen Floyd , Bradley McCredie , Kevin Franklin Reick , Hugh Rodney Stigdon , Jennifer Lane Vargus
发明人： Roger Ned Bailey , Michael Stephen Floyd , Bradley McCredie , Kevin Franklin Reick , Hugh Rodney Stigdon , Jennifer Lane Vargus
IPC分类号： G01R3128
CPC分类号： G06F11/27 , G01R31/319
摘要： The foregoing objects are achieved as is now described. A method and system for testing an integrated circuit are provided. A test substrate is provided which is manufactured by the same particular production technology for which the complex integrated circuit is designed. A pattern generator for generating test data and a result checker for comparing output data are embedded on the test substrate. Isolated portions of circuitry of the integrated circuit are selectively embedded onto the test substrate. The isolated portions of circuitry are subjected to testing by applying test data from the pattern generator to the isolated portions of circuitry. Errors in the isolated portions of circuitry are detected with the result checker by comparing data output from the isolated portions of circuitry with predetermined expected data, such that the integrated circuit is tested by susets, independently of testing the integrated circuit in its entirety.
摘要翻译： 如上所述实现上述目的。 提供了一种用于测试集成电路的方法和系统。 提供了由设计复合集成电路的相同特定生产技术制造的测试基板。 用于产生测试数据的图形发生器和用于比较输出数据的结果检查器嵌入在测试基板上。 集成电路的电路的隔离部分选择性地嵌入到测试基板上。 通过将来自图案发生器的测试数据应用到电路的隔离部分来对电路的隔离部分进行测试。 通过将来自电路的隔离部分的输出的数据与预定的预期数据进行比较来检测电路的隔离部分中的错误，使得集成电路被检测到，而不考虑集成电路的整体。
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73.发明授权Method and system for performing pseudo-random testing of an integrated circuit 失效用于执行集成电路的伪随机测试的方法和系统公开(公告)号：US06393594B1
公开(公告)日：2002-05-21
申请号：US09372698
申请日：1999-08-11
申请人： Carl J. Anderson , Michael Stephen Floyd , Larry Scott Leitner , Bradley McCredie , Kevin Franklin Reick , Jennifer Lane Vargus
发明人： Carl J. Anderson , Michael Stephen Floyd , Larry Scott Leitner , Bradley McCredie , Kevin Franklin Reick , Jennifer Lane Vargus
IPC分类号： G06F1100
CPC分类号： G01R31/318385 , G01R31/3183
摘要： A method and system for testing an integrated circuit. A test substrate is provided which is manufactured by the same particular production technology for which the integrated circuit is designed. A pattern generator for generating test data and a result checker for comparing output data are embedded on the test substrate. Isolated portions of circuitry of the integrated circuit are selectively embedded onto the test substrate. Test data from the pattern generator is applied to the isolated portions of circuitry under a first operating condition. The data output from the isolated portions of circuitry is selectively recorded into the result checker. The isolated portions of circuitry are then subjected to testing by applying test data from the pattern generator to the isolated portions of circuitry under a second operating condition. Errors in the isolated portions of circuitry are detected with the result checker by comparing data output from the isolated portions of circuitry with the selectively recorded data output, such that the integrated circuit is tested by subsets, independently of testing the integrated circuit in its entirety.
摘要翻译： 一种用于测试集成电路的方法和系统。 提供了通过设计集成电路的相同特定制造技术制造的测试基板。 用于产生测试数据的图形发生器和用于比较输出数据的结果检查器嵌入在测试基板上。 集成电路的电路的隔离部分选择性地嵌入到测试基板上。 来自图案发生器的测试数据被应用于在第一操作条件下的电路的隔离部分。 从电路的隔离部分输出的数据被选择性地记录到结果检查器中。 然后通过在第二操作条件下将来自图案发生器的测试数据应用到电路的隔离部分来对电路的隔离部分进行测试。 通过将来自电路的隔离部分的输出的数据与选择性记录的数据输出进行比较来检测电路的隔离部分中的错误，使得集成电路被子集测试，独立于集成电路的整体测试。
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74.发明授权System and method for phase alignment of a plurality of clock pulses when starting, stopping and pulsing clocks 失效当启动，停止和脉冲时钟时，多个时钟脉冲的相位对准的系统和方法公开(公告)号：US06333653B1
公开(公告)日：2001-12-25
申请号：US09435078
申请日：1999-11-04
IPC分类号： H03L700
摘要： The present invention is embodied in a clock controller for generating and controlling the phase alignment of a plurality of ratioed sub-clocks. A master clock is preferably input to a clock splitter to provide a plurality of slave clocks. Phase holds, generated from the slave clocks, are then used to gate each of the slave clocks to produce ratioed clocks that produce phase aligned clock pulses at integer factors of the master clock frequency. The clock controller controls the ratioed clocks by processing commands to start, stop, or pulse the ratioed clocks.
摘要翻译： 本发明体现在用于产生和控制多个比例子时钟的相位对准的时钟控制器中。 主时钟优选地被输入到时钟分配器以提供多个从时钟。 然后，从从时钟产生的相位保持用于门控每个从时钟以产生比率时钟，其以主时钟频率的整数因子产生相位对准的时钟脉冲。 时钟控制器通过处理启动，停止或脉冲比较时钟的命令来控制比较时钟。
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