公开(公告)号：US06393594B1

公开(公告)日：2002-05-21

申请号：US09372698

申请日：1999-08-11

申请人： Carl J. Anderson ,  Michael Stephen Floyd ,  Larry Scott Leitner ,  Bradley McCredie ,  Kevin Franklin Reick ,  Jennifer Lane Vargus

发明人： Carl J. Anderson ,  Michael Stephen Floyd ,  Larry Scott Leitner ,  Bradley McCredie ,  Kevin Franklin Reick ,  Jennifer Lane Vargus

IPC分类号： G06F1100

CPC分类号： G01R31/318385 ,  G01R31/3183

摘要： A method and system for testing an integrated circuit. A test substrate is provided which is manufactured by the same particular production technology for which the integrated circuit is designed. A pattern generator for generating test data and a result checker for comparing output data are embedded on the test substrate. Isolated portions of circuitry of the integrated circuit are selectively embedded onto the test substrate. Test data from the pattern generator is applied to the isolated portions of circuitry under a first operating condition. The data output from the isolated portions of circuitry is selectively recorded into the result checker. The isolated portions of circuitry are then subjected to testing by applying test data from the pattern generator to the isolated portions of circuitry under a second operating condition. Errors in the isolated portions of circuitry are detected with the result checker by comparing data output from the isolated portions of circuitry with the selectively recorded data output, such that the integrated circuit is tested by subsets, independently of testing the integrated circuit in its entirety.

摘要翻译： 一种用于测试集成电路的方法和系统。 提供了通过设计集成电路的相同特定制造技术制造的测试基板。 用于产生测试数据的图形发生器和用于比较输出数据的结果检查器嵌入在测试基板上。 集成电路的电路的隔离部分选择性地嵌入到测试基板上。 来自图案发生器的测试数据被应用于在第一操作条件下的电路的隔离部分。 从电路的隔离部分输出的数据被选择性地记录到结果检查器中。 然后通过在第二操作条件下将来自图案发生器的测试数据应用到电路的隔离部分来对电路的隔离部分进行测试。 通过将来自电路的隔离部分的输出的数据与选择性记录的数据输出进行比较来检测电路的隔离部分中的错误，使得集成电路被子集测试，独立于集成电路的整体测试。

公开(公告)号：US06438722B1

公开(公告)日：2002-08-20

申请号：US09372697

申请日：1999-08-11

申请人： Roger Ned Bailey ,  Michael Stephen Floyd ,  Bradley McCredie ,  Kevin Franklin Reick ,  Hugh Rodney Stigdon ,  Jennifer Lane Vargus

发明人： Roger Ned Bailey ,  Michael Stephen Floyd ,  Bradley McCredie ,  Kevin Franklin Reick ,  Hugh Rodney Stigdon ,  Jennifer Lane Vargus

IPC分类号： G01R3128

CPC分类号： G06F11/27 ,  G01R31/319

摘要： The foregoing objects are achieved as is now described. A method and system for testing an integrated circuit are provided. A test substrate is provided which is manufactured by the same particular production technology for which the complex integrated circuit is designed. A pattern generator for generating test data and a result checker for comparing output data are embedded on the test substrate. Isolated portions of circuitry of the integrated circuit are selectively embedded onto the test substrate. The isolated portions of circuitry are subjected to testing by applying test data from the pattern generator to the isolated portions of circuitry. Errors in the isolated portions of circuitry are detected with the result checker by comparing data output from the isolated portions of circuitry with predetermined expected data, such that the integrated circuit is tested by susets, independently of testing the integrated circuit in its entirety.

摘要翻译： 如上所述实现上述目的。 提供了一种用于测试集成电路的方法和系统。 提供了由设计复合集成电路的相同特定生产技术制造的测试基板。 用于产生测试数据的图形发生器和用于比较输出数据的结果检查器嵌入在测试基板上。 集成电路的电路的隔离部分选择性地嵌入到测试基板上。 通过将来自图案发生器的测试数据应用到电路的隔离部分来对电路的隔离部分进行测试。 通过将来自电路的隔离部分的输出的数据与预定的预期数据进行比较来检测电路的隔离部分中的错误，使得集成电路被检测到，而不考虑集成电路的整体。

公开(公告)号：US06633838B1

公开(公告)日：2003-10-14

申请号：US09435071

申请日：1999-11-04

申请人： Lakshminarayana Baba Arimilli ,  Michael Stephen Floyd ,  Larry Scott Leitner ,  Kevin F. Reick ,  Jennifer Lane Vargus

发明人： Lakshminarayana Baba Arimilli ,  Michael Stephen Floyd ,  Larry Scott Leitner ,  Kevin F. Reick ,  Jennifer Lane Vargus

IPC分类号： G06F1125

CPC分类号： G06F11/2236

摘要： The system and method of the present invention is embodied in a multi-state on-chip logic analyzer that is preferably integrated into a VLSI circuit. In general, the logic analyzer is preferably coupled to a multilevel trace array for storing event trace data generated by the logic analyzer. Input and output logic coupled to both the trace array and the logic analyzer allows reading or writing from or to the trace array, and programming of trigger and condition criteria for transitioning states within the logic analyzer. The logic analyzer has the capability match one or more programmable trigger events to satisfy one or more programmable conditions. Further, the logic analyzer preferably has the capability to initialize programmable conditions in desired states, and to store event trace data in an on-chip array for trace data reconstruction and analysis. Trace array input and output logic allows reading or writing from or to the trace array, and programming of trigger and condition criteria for transitioning states within the logic analyzer. Further, the trace array input and output logic is preferably accessible at both the wafer and component stage to allow for testing and debugging of the VLSI circuitry.

摘要翻译： 本发明的系统和方法体现在优选集成到VLSI电路中的多状态片上逻辑分析仪中。 通常，逻辑分析器优选地耦合到多级跟踪阵列，用于存储由逻辑分析器生成的事件跟踪数据。 耦合到跟踪阵列和逻辑分析仪的输入和输出逻辑器允许从跟踪数组读取或写入数据，以及对逻辑分析器内的转换状态的触发和条件标准进行编程。 逻辑分析仪具有匹配一个或多个可编程触发事件的能力，以满足一个或多个可编程条件。 此外，逻辑分析器优选地具有在期望状态下初始化可编程条件的能力，并且将事件跟踪数据存储在用于跟踪数据重建和分析的片上阵列中。 跟踪数组输入和输出逻辑允许从跟踪数组读取或写入数据，以及对逻辑分析器内的转换状态的触发和条件标准进行编程。 此外，迹线阵列输入和输出逻辑优选在晶片和元件级可访问以允许对VLSI电路进行测试和调试。