公开(公告)号：US06438722B1

公开(公告)日：2002-08-20

申请号：US09372697

申请日：1999-08-11

申请人： Roger Ned Bailey ,  Michael Stephen Floyd ,  Bradley McCredie ,  Kevin Franklin Reick ,  Hugh Rodney Stigdon ,  Jennifer Lane Vargus

发明人： Roger Ned Bailey ,  Michael Stephen Floyd ,  Bradley McCredie ,  Kevin Franklin Reick ,  Hugh Rodney Stigdon ,  Jennifer Lane Vargus

IPC分类号： G01R3128

CPC分类号： G06F11/27 ,  G01R31/319

摘要： The foregoing objects are achieved as is now described. A method and system for testing an integrated circuit are provided. A test substrate is provided which is manufactured by the same particular production technology for which the complex integrated circuit is designed. A pattern generator for generating test data and a result checker for comparing output data are embedded on the test substrate. Isolated portions of circuitry of the integrated circuit are selectively embedded onto the test substrate. The isolated portions of circuitry are subjected to testing by applying test data from the pattern generator to the isolated portions of circuitry. Errors in the isolated portions of circuitry are detected with the result checker by comparing data output from the isolated portions of circuitry with predetermined expected data, such that the integrated circuit is tested by susets, independently of testing the integrated circuit in its entirety.

摘要翻译： 如上所述实现上述目的。 提供了一种用于测试集成电路的方法和系统。 提供了由设计复合集成电路的相同特定生产技术制造的测试基板。 用于产生测试数据的图形发生器和用于比较输出数据的结果检查器嵌入在测试基板上。 集成电路的电路的隔离部分选择性地嵌入到测试基板上。 通过将来自图案发生器的测试数据应用到电路的隔离部分来对电路的隔离部分进行测试。 通过将来自电路的隔离部分的输出的数据与预定的预期数据进行比较来检测电路的隔离部分中的错误，使得集成电路被检测到，而不考虑集成电路的整体。

公开(公告)号：US06252264B1

公开(公告)日：2001-06-26

申请号：US09364739

申请日：1999-07-30

申请人： Roger Ned Bailey ,  Bradley McCredie ,  Michael Gerard Nealon ,  Hugh Rodney Stigdon

发明人： Roger Ned Bailey ,  Bradley McCredie ,  Michael Gerard Nealon ,  Hugh Rodney Stigdon

IPC分类号： H01L2710

CPC分类号： H01L25/0655 ,  H01L2224/16225

摘要： An integrated circuit chip has a first i/o set associated with a first edge of the chip and a second i/o set associated with a second edge of the chip. The first i/o set has a physical symmetry with respect to the second i/o set, to facilitate a number of the chips being interconnected in a ring to one another on a multi-chip module, with the chips symetrically disposed thereon. The chip has a bus interconnecting the first and second i/o sets for transmitting signals across the chip. The bus has regeneration circuitry for regenerating said signals traversing the chip.

摘要翻译： 集成电路芯片具有与芯片的第一边缘相关联的第一I / O集和与芯片的第二边缘相关联的第二I / O集合。 第一I / O组相对于第二i / o组具有物理对称性，以便于多芯片在多芯片模块上以彼此相互连接的多个芯片，其中芯片以对称方式设置在其上。 芯片具有互连第一和第二I / O组的总线，用于在芯片上传输信号。 总线具有用于再生穿过芯片的所述信号的再生电路。