公开(公告)号：US20190067407A1

公开(公告)日：2019-02-28

申请号：US15985485

申请日：2018-05-21

Applicant: Apple Inc.

Inventor： Cheng-Ho Yu ,  Abbas Jamshidi Roudbari ,  Shin-Hung Yeh ,  Sungki Lee ,  Ting-Kuo Chang ,  Yu Cheng Chen

IPC: H01L27/32 ,  G09G3/3225 ,  H01L51/52

CPC classification number: H01L27/3276 ,  G09G3/2092 ,  G09G3/3225 ,  G09G2310/0297 ,  H01L27/323 ,  H01L51/5237

Abstract: A display may have display driver circuitry. Signal routing lines may supply multiplexed signals from the display driver circuitry to demultiplexer circuitry. The demultiplexer circuitry may provide corresponding demultiplexed signals to the pixels over signal routing lines. The demultiplexer circuitry may have demultiplexer circuit blocks such as 1:N demultiplexer circuit blocks. Each of the demultiplexer circuit blocks may have the same area and layout. The demultiplexer circuit blocks may run across the width of the display. A first portion of the demultiplexer circuit blocks may extend in a straight line parallel to an edge of the active area. A second portion of the demultiplexer circuit blocks may be arranged in a staircase pattern that angles away from the first portion of demultiplexer circuit blocks.

公开(公告)号：US20190043418A1

公开(公告)日：2019-02-07

申请号：US15975390

申请日：2018-05-09

Applicant: Apple Inc.

Inventor： Warren S. Rieutort-Louis ,  Shyuan Yang ,  Tsung-Ting Tsai ,  Cheng-Ho Yu ,  Jae Won Choi ,  Bhadrinarayana Lalgudi Visweswaran ,  Abbas Jamshidi Roudbari ,  Ting-Kuo Chang

IPC: G09G3/3216 ,  G09G3/3283 ,  G09G3/3266 ,  H01L27/32

Abstract: A display may have rows and columns of pixels that form an active area for displaying images. A display driver integrated circuit may provide multiplexed data signals to demultiplexer circuitry in the display. The demultiplexer circuitry may demultiplex the data signals and provide the demultiplexed data signals to the pixels on data lines. Gate lines may control the loading of the data signals into the pixels. The display may have a length dimension and a width dimension that is shorter than the length dimension. The data lines may extend parallel to the width dimension and the gate lines may extend parallel to the length dimension such that there are more data lines than gate lines in the display. A notch that is free of pixels may extend into the active area. Data lines extending parallel to the width dimension of the display may be routed around the notch.

公开(公告)号：US10109240B2

公开(公告)日：2018-10-23

申请号：US15403070

申请日：2017-01-10

Applicant: Apple Inc.

Inventor： Shih Chang Chang ,  Keitaro Yamashita ,  Shin-Hung Yeh ,  Ting-Kuo Chang ,  Abbas Jamshidi Roudbari ,  Chin-Wei Lin

IPC: G09G3/3266 ,  G09G3/3291 ,  G09G5/18 ,  G06T19/00 ,  G09G3/36

Abstract: An electronic device may include a display such as a light-emitting diode display. The electronic device may be a head-mounted device that provides a virtual reality or augmented reality environment to a user. To reduce artifacts in the display, a display may be operable in both a normal scanning mode and a partial scanning mode. In the normal scanning mode, every row of the display may be scanned in each frame. In the partial scanning mode, only a subset of the rows of the display may be scanned in each frame. The display may have a higher refresh rate in the partial scanning mode than in the normal scanning mode. The gate driver circuitry may include a shift register that includes a plurality of register circuits. At least one register circuit may have a first input and a second input that is different than the first input.

公开(公告)号：US10101853B2

公开(公告)日：2018-10-16

申请号：US15260137

申请日：2016-09-08

Applicant: Apple Inc.

Inventor： Yu Cheng Chen ,  Keitaro Yamashita ,  Abbas Jamshidi Roudbari ,  Hirokazu Yamagata ,  Ting-Kuo Chang

IPC: H01L27/12 ,  G06F3/041 ,  G06F3/044

Abstract: Thin-film transistor circuitry for a display may include conductive layers such as transparent conductive layers and metal layers and may include dielectric layers. The dielectric layers may include buffer layers, interlayer dielectric, gate insulator, and organic planarization layers. The organic planarization layers may be patterned photolithographically to form vias, trenches, and other structures. Trenches may be formed by removing the planarization layer in a strip. When planarization material is removed for forming a trench or other structure, a step is formed in the planarization material. Metal lines such as data lines and other signal lines may cross steps in the planarization material. To prevent shorts between lines, a step may have protrusions that help eliminate metal etch residue. Vias may be reduced in depth by forming metal bumps and dielectric bumps under the vias and by forming other via structures.

公开(公告)号：US10019090B2

公开(公告)日：2018-07-10

申请号：US15238355

申请日：2016-08-16

Applicant: Apple Inc.

Inventor： Majid Gharghi ,  Sungki Lee ,  Abbas Jamshidi Roudbari ,  Shin-Hung Yeh ,  Ting-Kuo Chang ,  Yu Cheng Chen

IPC: G06F3/041 ,  G06F3/044 ,  G09G3/36 ,  G02F1/1333 ,  G02F1/1362 ,  G02F1/1343 ,  G02F1/1368

CPC classification number: G06F3/0412 ,  G02F1/13338 ,  G02F1/136286 ,  G06F3/0416 ,  G06F3/044 ,  G06F2203/04111 ,  G09G3/3648 ,  G09G2354/00

Abstract: A display may have an array of pixels. A transparent conductive layer may serve as a common voltage electrode layer and may distribute a common voltage to each of the pixels. Metal layers may be used to form routing structures. One of the metal layers may be patterned to form gate lines that distribute control signals to thin-film transistors in the pixels. Touch sensor circuitry may be coupled to horizontal and vertical capacitive touch sensor electrodes formed from the transparent conductive layer. A touch sensor signal border routing path in an inactive area of the display may have openings that run parallel to the gate lines and that each overlap one of the gate lines to reduce capacitive coupling between the gate lines and the touch sensor signal border routing path.

公开(公告)号：US09965063B2

公开(公告)日：2018-05-08

申请号：US14174471

申请日：2014-02-06

Applicant: Apple Inc.

Inventor： Abbas Jamshidi Roudbari ,  Shih-Chang Chang ,  Ting-Kuo Chang ,  Cheng-Ho Yu

IPC: G06F3/041 ,  G02F1/1333 ,  G02F1/136 ,  G02F1/1362

CPC classification number: G06F3/041 ,  G02F1/13338 ,  G02F1/13624 ,  G02F1/136286 ,  G02F2001/13606 ,  G06F3/0412 ,  G06F3/0416

Abstract: A touch screen display may have a color filter layer and a thin-film transistor layer. A layer of liquid crystal material may be located between the color filter layer and the thin-film transistor (TFT) layer. The TFT layer may include thin-film transistors formed on top of a glass substrate. Each display pixel in the TFT layer may include first and second TFTs coupled in series between a data line and a storage capacitor. The first TFT may have a gate that is coupled to a gate line. The second TFT may have a gate that is coupled to a control line that is different than the gate line. A global enable signal may be provided on the control line, where the enable signal is asserted during display intervals and is deasserted during touch intervals. The second TFT may be formed using a top-gate TFT or a bottom-gate TFT arrangement.

公开(公告)号：US20180075809A1

公开(公告)日：2018-03-15

申请号：US15403070

申请日：2017-01-10

Applicant: Apple Inc.

Inventor： Shih Chang Chang ,  Keitaro Yamashita ,  Shin-Hung Yeh ,  Ting-Kuo Chang ,  Abbas Jamshidi Roudbari ,  Chin-Wei Lin

IPC: G09G3/3266 ,  G09G3/3291 ,  G09G5/18

CPC classification number: G09G3/3266 ,  G06T19/006 ,  G09G3/3291 ,  G09G3/3677 ,  G09G5/18 ,  G09G2300/0809 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2310/04 ,  G09G2340/0414 ,  G09G2340/0435

Abstract: An electronic device may include a display such as a light-emitting diode display. The electronic device may be a head-mounted device that provides a virtual reality or augmented reality environment to a user. To reduce artifacts in the display, a display may be operable in both a normal scanning mode and a partial scanning mode. In the normal scanning mode, every row of the display may be scanned in each frame. In the partial scanning mode, only a subset of the rows of the display may be scanned in each frame. The display may have a higher refresh rate in the partial scanning mode than in the normal scanning mode. The gate driver circuitry may include a shift register that includes a plurality of register circuits. At least one register circuit may have a first input and a second input that is different than the first input.

公开(公告)号：US20170351379A1

公开(公告)日：2017-12-07

申请号：US15260137

申请日：2016-09-08

Applicant: Apple Inc.

Inventor： Yu Cheng Chen ,  Keitaro Yamashita ,  Abbas Jamshidi Roudbari ,  Hirokazu Yamagata ,  Ting-Kuo Chang

IPC: G06F3/041 ,  G06F3/044 ,  H01L27/12

CPC classification number: G06F3/0418 ,  G02F1/136286 ,  G02F2001/133357 ,  G02F2001/13629 ,  G06F3/0412 ,  G06F3/044 ,  G06F2203/04103 ,  G06F2203/04111 ,  H01L27/124

Abstract: Thin-film transistor circuitry for a display may include conductive layers such as transparent conductive layers and metal layers and may include dielectric layers. The dielectric layers may include buffer layers, interlayer dielectric, gate insulator, and organic planarization layers. The organic planarization layers may be patterned photolithographically to form vias, trenches, and other structures. Trenches may be formed by removing the planarization layer in a strip. When planarization material is removed for forming a trench or other structure, a step is formed in the planarization material. Metal lines such as data lines and other signal lines may cross steps in the planarization material. To prevent shorts between lines, a step may have protrusions that help eliminate metal etch residue. Vias may be reduced in depth by forming metal bumps and dielectric bumps under the vias and by forming other via structures.

公开(公告)号：US20170269744A1

公开(公告)日：2017-09-21

申请号：US15238355

申请日：2016-08-16

Applicant: Apple Inc.

Inventor： Majid Gharghi ,  Sungki Lee ,  Abbas Jamshidi Roudbari ,  Shin-Hung Yeh ,  Ting-Kuo Chang ,  Yu Cheng Chen

IPC: G06F3/041 ,  G09G3/36 ,  G02F1/1368 ,  G02F1/1362 ,  G02F1/1343 ,  G06F3/044 ,  G02F1/1333

CPC classification number: G06F3/0412 ,  G02F1/13338 ,  G02F1/136286 ,  G06F3/0416 ,  G06F3/044 ,  G06F2203/04111 ,  G09G3/3648 ,  G09G2354/00

Abstract: A display may have an array of pixels. A transparent conductive layer may serve as a common voltage electrode layer and may distribute a common voltage to each of the pixels. Metal layers may be used to form routing structures. One of the metal layers may be patterned to form gate lines that distribute control signals to thin-film transistors in the pixels. Touch sensor circuitry may be coupled to horizontal and vertical capacitive touch sensor electrodes formed from the transparent conductive layer. A touch sensor signal border routing path in an inactive area of the display may have openings that run parallel to the gate lines and that each overlap one of the gate lines to reduce capacitive coupling between the gate lines and the touch sensor signal border routing path.

公开(公告)号：US20170090236A1

公开(公告)日：2017-03-30

申请号：US14992894

申请日：2016-01-11

Applicant: Apple Inc.

Inventor： Shin-Hung Yeh ,  Sungki Lee ,  Abbas Jamshidi Roudbari ,  Cheng-Ho Yu ,  Jiun-Jye Chang ,  Ting-Kuo Chang ,  Yu Cheng Chen ,  Yun Wang

IPC: G02F1/1345 ,  G02F1/1343 ,  G02F1/1333 ,  G02F1/1368 ,  H01L29/786 ,  H01L27/12

CPC classification number: G02F1/13458 ,  G02F1/1368 ,  G02F2001/133357 ,  H01L27/124 ,  H01L27/1244 ,  H01L27/1248 ,  H01L29/78606 ,  H01L29/78618

Abstract: A display may have an array of pixels that forms an active display area for displaying images. An inactive border area of the display may have contact pads to which integrated circuits and flexible printed circuits may be attached. The contact pads may be free of organic planarization layers and may be formed from multiple stacked conductive layers. The inactive portion of the display may include electrostatic discharge protection structures associated with the pads, metal layers that form signal paths extending between the pads and the pixels, interlayer dielectric layers for protecting the metal layers that form the signal paths, polysilicon footer structures that help prevent undercutting of gate insulator material in the vicinity of the pads, and other pad and signal line structures.