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    METHODS AND APPARATUSES FOR PACKAGING AN ULTRASOUND-ON-A-CHIP
    72.
    发明申请
    METHODS AND APPARATUSES FOR PACKAGING AN ULTRASOUND-ON-A-CHIP 有权

    公开(公告)号：US20210296195A1

    公开(公告)日：2021-09-23

    申请号：US17191829

    申请日：2021-03-04

    Applicant: Butterfly Network, Inc.

    Inventor： Jianwei Liu ,  Keith G. Fife

    IPC: H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  A61B8/00

    Abstract: Described herein are methods and apparatuses for packaging an ultrasound-on-a-chip. An ultrasound-on-a-chip may be coupled to a redistribution layer and to an interposer layer. Encapsulation may encapsulate the ultrasound-on-a-chip device and first metal pillars may extend through the encapsulation and electrically couple to the redistribution layer. Second metal pillars may extend through the interposer layer. The interposer layer may include aluminum nitride. The first metal pillars may be electrically coupled to the second metal pillars. A printed circuit board may be coupled to the interposer layer.

    Methods and apparatuses for packaging an ultrasound-on-a-chip
    74.
    发明授权
    Methods and apparatuses for packaging an ultrasound-on-a-chip 有权

    公开(公告)号：US11018068B2

    公开(公告)日：2021-05-25

    申请号：US16502553

    申请日：2019-07-03

    Applicant: Butterfly Network, Inc.

    Inventor： Jianwei Liu ,  Keith G. Fife

    IPC: H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  A61B8/00

    Abstract: Described herein are methods and apparatuses for packaging an ultrasound-on-a-chip. An ultrasound-on-a-chip may be coupled to a redistribution layer and to an interposer layer. Encapsulation may encapsulate the ultrasound-on-a-chip device and first metal pillars may extend through the encapsulation and electrically couple to the redistribution layer. Second metal pillars may extend through the interposer layer. The interposer layer may include aluminum nitride. The first metal pillars may be electrically coupled to the second metal pillars. A printed circuit board may be coupled to the interposer layer.

    VERTICAL PACKAGING FOR ULTRASOUND-ON-A-CHIP AND RELATED METHODS
    75.
    发明申请
    VERTICAL PACKAGING FOR ULTRASOUND-ON-A-CHIP AND RELATED METHODS 有权

    公开(公告)号：US20210113188A1

    公开(公告)日：2021-04-22

    申请号：US17088336

    申请日：2020-11-03

    Applicant: Butterfly Network, Inc.

    Inventor： Keith G. Fife ,  Jianwei Liu

    IPC: A61B8/00 ,  H01L41/293 ,  H01L41/113

    Abstract: Vertical packaging configurations for ultrasound chips are described. Vertical packaging may involve use of integrated interconnects other than wires for wire bonding. Examples of such integrated interconnects include edge-contact vias, through silicon vias and conductive pillars. Edge-contact vias are vias defined in a trench formed in the ultrasound chip. Multiple vias may be provided for each trench, thus increasing the density of vias. Such vias enable electric access to the ultrasound transducers. Through silicon vias are formed through the silicon handle and provide access from the bottom surface of the ultrasound chip. Conductive pillars, including copper pillars, are disposed around the perimeter of an ultrasound chip and provide access to the ultrasound transducers from the top surface of the chip. Use of these types of packaging techniques can enable a substantial reduction in the dimensions of an ultrasound device.

    PACKAGING STRUCTURES AND PACKAGING METHODS FOR ULTRASOUND-ON-CHIP DEVICES
    78.
    发明申请
    PACKAGING STRUCTURES AND PACKAGING METHODS FOR ULTRASOUND-ON-CHIP DEVICES 审中-公开

    公开(公告)号：US20200239299A1

    公开(公告)日：2020-07-30

    申请号：US16774956

    申请日：2020-01-28

    Applicant: Butterfly Network, Inc.

    Inventor： Jianwei Liu ,  Keith G. Fife

    IPC: B81B7/00 ,  B06B1/02 ,  B81C1/00

    Abstract: A method of forming a multiple layer, hybrid interposer structure includes forming a plurality of first openings through a substrate, the substrate comprising a heat spreading material; forming a first metal material within the plurality of first openings and on top and bottom surfaces of the substrate; patterning the first metal material; forming a dielectric layer over the patterned first metal material; forming a plurality of second openings within the dielectric layer to expose portions of the patterned first metal material on the top and bottom surfaces of the substrate; filling the plurality of second openings with a second metal material, in contact with the exposed portions of the patterned first metal material; forming a third metal material on the top and bottom surfaces of the substrate, the third metal material in contact with the second metal material and the dielectric layer; and patterning the third metal material.

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