摘要:
An error detection and correction processor computes in real time successive approximations to a Galois field error locator polynomial and a Galois field error evaluator polynomial from the remainder or syndrome polynomial of a received block of data by executing successive iterations of a recursive algorithm. The processor stores each coefficient of the polynomials in an individually addressable memory location. During each iteration, the processor operates on successive ones of the coefficients of each polynomial in successive memory access cycles to compute a new version of the coefficient which replaces the old one in memory.
摘要:
The present disclosure is directed to a system for dynamically adaptive caching. The system includes a storage device having a physical capacity for storing data received from a host. The system may also include a control module for receiving data from the host and compressing the data to a compressed data size. Alternatively, the data may also be compressed by the storage device. The control module may be configured for determining an amount of available space on the storage device and also determining a reclaimed space, the reclaimed space being according to a difference between the size of the data received from the host and the compressed data size. The system may also include an interface module for presenting a logical capacity to the host. The logical capacity has a variable size and may include at least a portion of the reclaimed space.
摘要:
The present disclosure is directed to a system for dynamically adaptive caching. The system includes a storage device having a physical capacity for storing data received from a host. The system may also include a control module for receiving data from the host and compressing the data to a compressed data size. Alternatively, the data may also be compressed by the storage device. The control module may be configured for determining an amount of available space on the storage device and also determining a reclaimed space, the reclaimed space being according to a difference between the size of the data received from the host and the compressed data size. The system may also include an interface module for presenting a logical capacity to the host. The logical capacity has a variable size and may include at least a portion of the reclaimed space.
摘要:
Disclosed is a hierarchy of individual schedulers with multiple scheduling lanes for scheduling items, such as, but not limited to packets or indications thereof, such that different classes of priority items can be propagated through the hierarchy of schedulers accordingly. A pipeline scheduler typically includes a root scheduler and one or more layers of schedulers with each of these layers including at least one scheduler. Each scheduler is configured to maintain items of different scheduling categories received from each of the particular scheduler's immediate children schedulers within the pipeline scheduler if any and from each immediate external source coupled to the particular scheduler if any, and to schedule the sending of the items of the different scheduling categories currently maintained to its parent schedule or external scheduler client. The items may correspond to packets, indications of packets, or any other entity.
摘要:
A method and system for providing delay bound and prioritized packet dropping are disclosed. The system limits the size of a queue configured to deliver packets in FIFO order by a threshold based on a specified delay bound. Received packets are queued if the threshold is not exceeded. If the threshold is exceeded, a packet having a precedence level less than that of the precedence level of the received packet is dropped. If all packets in the queue have a precedence level greater than that of the packet received, then the received packet is dropped if the threshold is exceeded.
摘要:
Methods, apparatus, data structures, computer-readable media, and mechanisms may include or be used with a hierarchy of schedules with propagation of minimum guaranteed scheduling rates among scheduling layers in a hierarchical schedule. The minimum guaranteed scheduling rate for a parent schedule entry is typically based on the summation of the minimum guaranteed scheduling rates of its immediate child schedule entries. This propagation of minimum rate scheduling guarantees for a class of traffic can be dynamic (e.g., based on the active traffic for this class of traffic, active services for this class of traffic), or statically configured. One embodiment also includes multiple scheduling lanes for scheduling items, such as, but not limited to packets or indications thereof, such that different categories of traffic (e.g., propagated minimum guaranteed scheduling rate, non-propagated minimum guaranteed scheduling rate, high priority, excess rate, etc.) of scheduled items can be propagated through the hierarchy of schedules accordingly without being blocked behind a lower priority or different type of traffic.
摘要:
Methods and apparatus are disclosed for simultaneously scheduling multiple priorities of packets, such as in systems having a non-blocking switching fabric. In one implementation, the maximum bandwidth which a particular input can send is identified. During a scheduling cycle, a current bandwidth desired for a first priority of traffic is identified, which leaves the remaining bandwidth available for a second priority of traffic without affecting the bandwidth allocated to the first priority of traffic. By determining these bandwidth amounts at each iteration of a scheduling cycle, multiple priorities of traffic can be simultaneously scheduled. This approach may be used by a wide variety of scheduling approaches, such as, but not limited to using a SLIP algorithm or variant thereof. When used in conjunction with a SLIP algorithm, the current desired bandwidths typically correspond to high and low priority requests.
摘要:
Methods and apparatus are disclosed for identifying a variable number of items first in sequence from a variable starting position which may be particularly useful by packet or other scheduling mechanisms, such as, but not limited to the SLIP/I SLIP scheduling algorithms or variants thereof. Each of the groups of items is typically identified with a number of items the group desires to be selected. Based on an identified starting position, a progressive sum value is initialized, with progressive sum values corresponding to successive groups of items in the sequence being adjusted typically based on the corresponding number of items each successive group desires to be selected. The number of items a particular group is authorized to select can then be determined, such as, but not limited to, by being based on its corresponding progressive sum value, the progressive sum value of the immediately prior group in the sequence, and its desired number of items to be selected.
摘要翻译:公开了用于从可能由分组或其他调度机制特别有用的可变起始位置顺序地识别可变数量的项目的方法和装置,诸如但不限于SLIP / I SLIP调度算法或其变体。 每个项目组中的每一组通常用群组希望选择的项目来标识。 基于所识别的开始位置,初始化渐进和值,其中对应于序列中的连续组的项目的渐进和值通常基于每个连续组期望选择的对应数量来调整。 然后可以确定特定组被授权选择的项目的数量,例如但不限于通过基于其对应的渐进和值,序列中紧前的组的渐进和值和其期望的 要选择的项目数量
摘要:
Processing a packet typically includes enqueuing the packet on to a queue when it arrives at a device, and then at some later time under control of the scheduler, dequeuing the packet for transmission. The scheduler needs some representation of the packet length for its uses when dequeuing. By storing the packet length as an adjusted packet length containing fewer bits, the scheduler and any storage of the packets lengths in the queues are reduced in complexity/size. One implementation maintains a residue amount corresponding to one or more packet queues or streams of packets. The residue amount is updated to maintain a forward looking or lagging behind indication of the error induced by this approximation. An adjusted packet length for the packet is determined based on its actual packet length and the residue amount. The residue amount is accordingly updated to reduce any long term error induced by using the adjusted packet lengths.
摘要:
A system and method for designing a digital circuit. The method includes identifying a single phase digital circuit implementing a desired function and operating at a first rate and determining a number of copies of the single phase digital circuit that are required for the digital circuit. Each copy of the single phase circuit is a phase and operates at a lesser rate wherein the sum of the lesser rates is less than or equal to the first rate. The method includes identifying the state devices within the single phase digital circuit, replacing each state device in the single phase digital circuit with a multiphase state saving device and providing control signals to each multiphase state saving device to control the reading and writing of state information for each phase into and out of a respective multiphase state saving device.