Hard-wired serial Galois field decoder
    71.
    发明授权
    Hard-wired serial Galois field decoder 失效
    硬线串行伽罗瓦域解码器

    公开(公告)号:US4833678A

    公开(公告)日:1989-05-23

    申请号:US76579

    申请日:1987-07-22

    申请人: Earl T. Cohen

    发明人: Earl T. Cohen

    IPC分类号: G06F7/72 H03M13/15

    CPC分类号: H03M13/151 G06F7/724

    摘要: An error detection and correction processor computes in real time successive approximations to a Galois field error locator polynomial and a Galois field error evaluator polynomial from the remainder or syndrome polynomial of a received block of data by executing successive iterations of a recursive algorithm. The processor stores each coefficient of the polynomials in an individually addressable memory location. During each iteration, the processor operates on successive ones of the coefficients of each polynomial in successive memory access cycles to compute a new version of the coefficient which replaces the old one in memory.

    摘要翻译: 错误检测和校正处理器通过执行递归算法的连续迭代,从接收到的数据块的余数或校正子多项式实时地计算伽罗瓦域误差定位器多项式和伽罗瓦域误差估计器多项式的逐次逼近。 处理器将多项式的每个系数存储在单独可寻址的存储器位置中。 在每次迭代期间,处理器在连续的存储器访问周期中对每个多项式的连续的系数进行操作,以计算在存储器中替换旧的系数的新版本。

    System for dynamically adaptive caching
    72.
    发明授权
    System for dynamically adaptive caching 有权
    用于动态自适应缓存的系统

    公开(公告)号:US09158695B2

    公开(公告)日:2015-10-13

    申请号:US13566204

    申请日:2012-08-03

    IPC分类号: G06F12/00 G06F12/08

    CPC分类号: G06F12/0871 G06F2212/401

    摘要: The present disclosure is directed to a system for dynamically adaptive caching. The system includes a storage device having a physical capacity for storing data received from a host. The system may also include a control module for receiving data from the host and compressing the data to a compressed data size. Alternatively, the data may also be compressed by the storage device. The control module may be configured for determining an amount of available space on the storage device and also determining a reclaimed space, the reclaimed space being according to a difference between the size of the data received from the host and the compressed data size. The system may also include an interface module for presenting a logical capacity to the host. The logical capacity has a variable size and may include at least a portion of the reclaimed space.

    摘要翻译: 本公开涉及用于动态自适应缓存的系统。 该系统包括具有用于存储从主机接收的数据的物理容量的存储设备。 该系统还可以包括用于从主机接收数据并将数据压缩到压缩数据大小的控制模块。 或者,数据也可以被存储设备压缩。 控制模块可以被配置用于确定存储设备上的可用空间量,并且还确定回收空间,所述回收空间根据从主机接收的数据的大小与压缩数据大小之间的差异。 该系统还可以包括用于向主机呈现逻辑容量的接口模块。 逻辑容量具有可变大小并且可以包括至少部分回收空间。

    SYSTEM FOR DYNAMICALLY ADAPTIVE CACHING
    73.
    发明申请
    SYSTEM FOR DYNAMICALLY ADAPTIVE CACHING 有权
    用于动态自适应高速缓存的系统

    公开(公告)号:US20130042064A1

    公开(公告)日:2013-02-14

    申请号:US13566204

    申请日:2012-08-03

    IPC分类号: G06F12/08

    CPC分类号: G06F12/0871 G06F2212/401

    摘要: The present disclosure is directed to a system for dynamically adaptive caching. The system includes a storage device having a physical capacity for storing data received from a host. The system may also include a control module for receiving data from the host and compressing the data to a compressed data size. Alternatively, the data may also be compressed by the storage device. The control module may be configured for determining an amount of available space on the storage device and also determining a reclaimed space, the reclaimed space being according to a difference between the size of the data received from the host and the compressed data size. The system may also include an interface module for presenting a logical capacity to the host. The logical capacity has a variable size and may include at least a portion of the reclaimed space.

    摘要翻译: 本公开涉及用于动态自适应缓存的系统。 该系统包括具有用于存储从主机接收的数据的物理容量的存储装置。 该系统还可以包括用于从主机接收数据并将数据压缩到压缩数据大小的控制模块。 或者,数据也可以被存储设备压缩。 控制模块可以被配置用于确定存储设备上的可用空间量,并且还确定回收空间,所述回收空间根据从主机接收的数据的大小与压缩数据大小之间的差异。 该系统还可以包括用于向主机呈现逻辑容量的接口模块。 逻辑容量具有可变大小并且可以包括至少部分回收空间。

    Pipeline scheduler including a hierarchy of schedulers and multiple scheduling lanes
    74.
    发明授权
    Pipeline scheduler including a hierarchy of schedulers and multiple scheduling lanes 有权
    流水线调度器包括调度器和多个调度通道的层次结构

    公开(公告)号:US07876763B2

    公开(公告)日:2011-01-25

    申请号:US10913055

    申请日:2004-08-05

    IPC分类号: H04L12/28

    摘要: Disclosed is a hierarchy of individual schedulers with multiple scheduling lanes for scheduling items, such as, but not limited to packets or indications thereof, such that different classes of priority items can be propagated through the hierarchy of schedulers accordingly. A pipeline scheduler typically includes a root scheduler and one or more layers of schedulers with each of these layers including at least one scheduler. Each scheduler is configured to maintain items of different scheduling categories received from each of the particular scheduler's immediate children schedulers within the pipeline scheduler if any and from each immediate external source coupled to the particular scheduler if any, and to schedule the sending of the items of the different scheduling categories currently maintained to its parent schedule or external scheduler client. The items may correspond to packets, indications of packets, or any other entity.

    摘要翻译: 公开了具有用于调度项目的多个调度通道的单独调度器的层级,诸如但不限于分组或其指示,使得不同类别的优先级项目可以相应地通过调度器的分层传播。 流水线调度器通常包括根调度器和一个或多个调度器层,其中每个层包括至少一个调度器。 每个调度器被配置为维护从流水线调度器内的每个特定调度器的直接子调度器接收的不同调度类别的项目,如果有的话,并且从每个立即外部源耦合到特定调度器(如果有的话),并且调度发送 当前维护到其父计划或外部调度程序客户端的不同调度类别。 这些项目可以对应于分组,分组的指示或任何其他实体。

    Propagation of minimum guaranteed scheduling rates among scheduling layers in a hierarchical schedule
    76.
    发明授权
    Propagation of minimum guaranteed scheduling rates among scheduling layers in a hierarchical schedule 有权
    在分级调度中调度层之间的最小保证调度速率的传播

    公开(公告)号:US07522609B2

    公开(公告)日:2009-04-21

    申请号:US11022246

    申请日:2004-12-23

    IPC分类号: H04L12/56

    摘要: Methods, apparatus, data structures, computer-readable media, and mechanisms may include or be used with a hierarchy of schedules with propagation of minimum guaranteed scheduling rates among scheduling layers in a hierarchical schedule. The minimum guaranteed scheduling rate for a parent schedule entry is typically based on the summation of the minimum guaranteed scheduling rates of its immediate child schedule entries. This propagation of minimum rate scheduling guarantees for a class of traffic can be dynamic (e.g., based on the active traffic for this class of traffic, active services for this class of traffic), or statically configured. One embodiment also includes multiple scheduling lanes for scheduling items, such as, but not limited to packets or indications thereof, such that different categories of traffic (e.g., propagated minimum guaranteed scheduling rate, non-propagated minimum guaranteed scheduling rate, high priority, excess rate, etc.) of scheduled items can be propagated through the hierarchy of schedules accordingly without being blocked behind a lower priority or different type of traffic.

    摘要翻译: 方法,装置,数据结构,计算机可读介质和机制可以包括或者与分级调度中的调度层中具有最小保证调度速率的传播的调度层次结合使用。 父计划条目的最小保证调度速率通常基于其直接子进程表项的最小保证调度速率的总和。 对一类流量的最小速率调度保证的这种传播可以是动态的(例如,基于该类流量的活动流量,用于该类流量的活动服务)或静态配置。 一个实施例还包括用于调度项目的多个调度通道,诸如但不限于分组或其指示,使得不同类别的业务(例如,传播的最小保证调度速率,非传播最小保证调度速率,高优先级,超量 调度项目的速率等)可以相应地通过调度层次传播,而不会被阻塞在较低优先级或不同类型的业务量之上。

    Methods and apparatus for simultaneously scheduling multiple priorities of packets
    77.
    发明授权
    Methods and apparatus for simultaneously scheduling multiple priorities of packets 有权
    用于同时调度数据包的多个优先级的方法和装置

    公开(公告)号:US07453898B1

    公开(公告)日:2008-11-18

    申请号:US10339032

    申请日:2003-01-09

    IPC分类号: H04L12/26 H04L12/56

    摘要: Methods and apparatus are disclosed for simultaneously scheduling multiple priorities of packets, such as in systems having a non-blocking switching fabric. In one implementation, the maximum bandwidth which a particular input can send is identified. During a scheduling cycle, a current bandwidth desired for a first priority of traffic is identified, which leaves the remaining bandwidth available for a second priority of traffic without affecting the bandwidth allocated to the first priority of traffic. By determining these bandwidth amounts at each iteration of a scheduling cycle, multiple priorities of traffic can be simultaneously scheduled. This approach may be used by a wide variety of scheduling approaches, such as, but not limited to using a SLIP algorithm or variant thereof. When used in conjunction with a SLIP algorithm, the current desired bandwidths typically correspond to high and low priority requests.

    摘要翻译: 公开了用于同时调度分组的多个优先级的方法和装置,例如在具有非阻塞交换结构的系统中。 在一个实现中,识别特定输入可以发送的最大带宽。 在调度周期期间,识别业务的第一优先级所期望的当前带宽,这使剩余带宽可用于业务的第二优先级,而不影响分配给业务的第一优先级的带宽。 通过在调度周期的每次迭代中确定这些带宽量,可以同时调度业务的多个优先级。 这种方法可以通过各种调度方法使用,诸如但不限于使用SLIP算法或其变体。 当与SLIP算法结合使用时,当前期望的带宽通常对应于高优先级请求和低优先级请求。

    Methods and apparatus for identifying a variable number of items first in sequence from a variable starting position which may be particularly useful by packet or other scheduling mechanisms
    78.
    发明授权
    Methods and apparatus for identifying a variable number of items first in sequence from a variable starting position which may be particularly useful by packet or other scheduling mechanisms 有权
    从可能由分组或其他调度机制特别有用的可变开始位置顺序地识别可变数目的项目的方法和装置

    公开(公告)号:US07408937B1

    公开(公告)日:2008-08-05

    申请号:US10338985

    申请日:2003-01-09

    IPC分类号: H04L12/56

    摘要: Methods and apparatus are disclosed for identifying a variable number of items first in sequence from a variable starting position which may be particularly useful by packet or other scheduling mechanisms, such as, but not limited to the SLIP/I SLIP scheduling algorithms or variants thereof. Each of the groups of items is typically identified with a number of items the group desires to be selected. Based on an identified starting position, a progressive sum value is initialized, with progressive sum values corresponding to successive groups of items in the sequence being adjusted typically based on the corresponding number of items each successive group desires to be selected. The number of items a particular group is authorized to select can then be determined, such as, but not limited to, by being based on its corresponding progressive sum value, the progressive sum value of the immediately prior group in the sequence, and its desired number of items to be selected.

    摘要翻译: 公开了用于从可能由分组或其他调度机制特别有用的可变起始位置顺序地识别可变数量的项目的方法和装置,诸如但不限于SLIP / I SLIP调度算法或其变体。 每个项目组中的每一组通常用群组希望选择的项目来标识。 基于所识别的开始位置,初始化渐进和值,其中对应于序列中的连续组的项目的渐进和值通常基于每个连续组期望选择的对应数量来调整。 然后可以确定特定组被授权选择的项目的数量,例如但不限于通过基于其对应的渐进和值,序列中紧前的组的渐进和值和其期望的 要选择的项目数量

    Residue-based encoding of packet lengths of particular use in processing and scheduling packets
    79.
    发明授权
    Residue-based encoding of packet lengths of particular use in processing and scheduling packets 有权
    在处理和调度数据包中特别使用的分组长度的基于残差的编码

    公开(公告)号:US07349418B1

    公开(公告)日:2008-03-25

    申请号:US10617539

    申请日:2003-07-11

    申请人: Earl T. Cohen

    发明人: Earl T. Cohen

    摘要: Processing a packet typically includes enqueuing the packet on to a queue when it arrives at a device, and then at some later time under control of the scheduler, dequeuing the packet for transmission. The scheduler needs some representation of the packet length for its uses when dequeuing. By storing the packet length as an adjusted packet length containing fewer bits, the scheduler and any storage of the packets lengths in the queues are reduced in complexity/size. One implementation maintains a residue amount corresponding to one or more packet queues or streams of packets. The residue amount is updated to maintain a forward looking or lagging behind indication of the error induced by this approximation. An adjusted packet length for the packet is determined based on its actual packet length and the residue amount. The residue amount is accordingly updated to reduce any long term error induced by using the adjusted packet lengths.

    摘要翻译: 处理数据包通常包括:当数据包到达某个设备时将数据包加入到队列中,然后在调度程序的控制下稍后的一段时间将该数据包出队进行传输。 调度程序需要在出队时使用其数据包长度的一些表示。 通过将分组长度存储为包含较少比特的调整分组长度,调度器和队列中的分组长度的任何存储器的复杂度/大小都被减少。 一个实现保持对应于一个或多个分组队列或分组流的残留量。 残留量被更新以保持由该近似引起的误差的向前看或滞后的指示。 基于其实际分组长度和剩余量确定分组的经调整分组长度。 因此,残留量被更新以减少通过使用调整的分组长度而引起的任何长期误差。

    Digital designs optimized with time division multiple access technology

    公开(公告)号:US06556045B2

    公开(公告)日:2003-04-29

    申请号:US09826563

    申请日:2001-04-04

    申请人: Earl T. Cohen

    发明人: Earl T. Cohen

    IPC分类号: G06F738

    摘要: A system and method for designing a digital circuit. The method includes identifying a single phase digital circuit implementing a desired function and operating at a first rate and determining a number of copies of the single phase digital circuit that are required for the digital circuit. Each copy of the single phase circuit is a phase and operates at a lesser rate wherein the sum of the lesser rates is less than or equal to the first rate. The method includes identifying the state devices within the single phase digital circuit, replacing each state device in the single phase digital circuit with a multiphase state saving device and providing control signals to each multiphase state saving device to control the reading and writing of state information for each phase into and out of a respective multiphase state saving device.