公开(公告)号：US07408937B1

公开(公告)日：2008-08-05

申请号：US10338985

申请日：2003-01-09

申请人： Earl T. Cohen ,  Tony Lee Werner

发明人： Earl T. Cohen ,  Tony Lee Werner

IPC分类号： H04L12/56

CPC分类号： H04L47/6255 ,  H04L47/50 ,  H04L47/522 ,  H04L2012/5679 ,  H04L2012/5681

摘要： Methods and apparatus are disclosed for identifying a variable number of items first in sequence from a variable starting position which may be particularly useful by packet or other scheduling mechanisms, such as, but not limited to the SLIP/I SLIP scheduling algorithms or variants thereof. Each of the groups of items is typically identified with a number of items the group desires to be selected. Based on an identified starting position, a progressive sum value is initialized, with progressive sum values corresponding to successive groups of items in the sequence being adjusted typically based on the corresponding number of items each successive group desires to be selected. The number of items a particular group is authorized to select can then be determined, such as, but not limited to, by being based on its corresponding progressive sum value, the progressive sum value of the immediately prior group in the sequence, and its desired number of items to be selected.

摘要翻译： 公开了用于从可能由分组或其他调度机制特别有用的可变起始位置顺序地识别可变数量的项目的方法和装置，诸如但不限于SLIP / I SLIP调度算法或其变体。 每个项目组中的每一组通常用群组希望选择的项目来标识。 基于所识别的开始位置，初始化渐进和值，其中对应于序列中的连续组的项目的渐进和值通常基于每个连续组期望选择的对应数量来调整。 然后可以确定特定组被授权选择的项目的数量，例如但不限于通过基于其对应的渐进和值，序列中紧前的组的渐进和值和其期望的 要选择的项目数量

公开(公告)号：US07159102B2

公开(公告)日：2007-01-02

申请号：US10869760

申请日：2004-06-15

申请人： Naohiko Irie ,  Tony Lee Werner

发明人： Naohiko Irie ,  Tony Lee Werner

IPC分类号： G06F9/38

CPC分类号： G06F9/3885 ,  G06F9/30058 ,  G06F9/322 ,  G06F9/3806 ,  G06F9/3842 ,  G06F9/3846

摘要： A branch control memory store branch instructions which are adapted for optimizing performance of programs run on electronic processors. Flexible instruction parameter fields permit a variety of new branch control and branch instruction implementations best suited for a particular computing environment. These instructions also have separate prediction bits, which are used to optimize loading of target instruction buffers in advance of program execution, so that a pipeline within the processor achieves superior performance during actual program execution.

摘要翻译： 分支控制存储器存储适于优化在电子处理器上运行的程序的性能的分支指令。 灵活的指令参数字段允许最适合特定计算环境的各种新的分支控制和分支指令实现。 这些指令还具有单独的预测位，其用于在程序执行之前优化目标指令缓冲器的加载，使得处理器内的流水线在实际程序执行期间实现优异的性能。

公开(公告)号：US06389531B1

公开(公告)日：2002-05-14

申请号：US09690500

申请日：2000-10-17

申请人： Naohiko Irle ,  Tony Lee Werner

发明人： Naohiko Irle ,  Tony Lee Werner

IPC分类号： G06F938

CPC分类号： G06F9/3804 ,  G06F9/30058 ,  G06F9/322 ,  G06F9/3842 ,  G06F9/3846 ,  G06F9/3885

摘要： A processor is provided with an improved instruction buffer, branch target instruction memory, branch target address memory and instruction decoder adapted for handling branch instructions so as to reduce latencies. A branch operation uses both a program branch control instruction (executed in advance to determine the branch target instruction address) and either a conditional or unconditional branch instruction associated with a conditional/unconditional branch target instruction respectively. The conditional/unconditional branch instruction and the program branch control instruction both include separate prediction indicators used by the instruction decoder for initiating a loading and speculatively pre-loading of instructions for execution in the processor.

摘要翻译： 处理器设置有改进的指令缓冲器，分支目标指令存储器，分支目标地址存储器和适于处理分支指令以便减少延迟的指令解码器。 分支操作分别使用程序分支控制指令（预先执行以确定分支目标指令地址）以及与条件/无条件分支目标指令相关联的条件或无条件分支指令。 条件/无条件分支指令和程序分支控制指令都包括由指令解码器使用的单独的预测指示符，用于启动加载并推测性地预加载用于在处理器中执行的指令。

公开(公告)号：US06772325B1

公开(公告)日：2004-08-03

申请号：US09410682

申请日：1999-10-01

申请人： Naohiko Irie ,  Tony Lee Werner

发明人： Naohiko Irie ,  Tony Lee Werner

IPC分类号： G06F938

CPC分类号： G06F9/3885 ,  G06F9/30058 ,  G06F9/322 ,  G06F9/3806 ,  G06F9/3842 ,  G06F9/3846

摘要： A processor is disclosed utilizing improved branch control and branch instructions for optimizing performance of programs run on such processors. Flexible instruction parameter fields permit a variety of new branch control and branch instruction implementations best suited for a particular computing environment. These instructions also have separate prediction bits, which are used to optize loading of target instruction buffers in advance of program execution, so that a pipeline within the processor achieves superior performance during actual program execution.

摘要翻译： 公开了利用改进的分支控制和分支指令来优化在这种处理器上运行的程序的性能的处理器。 灵活的指令参数字段允许最适合特定计算环境的各种新的分支控制和分支指令实现。 这些指令还具有单独的预测位，其用于在程序执行之前优化加载目标指令缓冲器，使得处理器内的流水线在实际程序执行期间实现优异的性能。

公开(公告)号：US06449712B1

公开(公告)日：2002-09-10

申请号：US09410851

申请日：1999-10-01

申请人： Naohiko Irie ,  Tony Lee Werner ,  Chih-Jui Peng ,  Sebastian H. Ziesler ,  Jackie A. Freeman ,  Sivaram Krishnan

发明人： Naohiko Irie ,  Tony Lee Werner ,  Chih-Jui Peng ,  Sebastian H. Ziesler ,  Jackie A. Freeman ,  Sivaram Krishnan

IPC分类号： G06F9455

CPC分类号： G06F9/30174 ,  G06F9/30058 ,  G06F9/3842

摘要： A processor element, structured to execute a 32-bit fixed length instruction set architecture, is backward compatible for executing a 16-bit fixed length instruction set architecture by translating each of the 16-bit instructions into a sequence of one or more 32-bit instructions. The 32-bit instruction set architecture includes “prepare to branch” instructions that allow target addresses for branch instructions to be set up in advance of the branch. The 32-bit prepare to branch and branch instructions are combined to execute a 16-bit branch instruction coupled with a 16-bit Delay Slot instruction.

摘要翻译： 构造为执行32位固定长度指令集体系结构的处理器元件向后兼容，用于通过将16位指令中的每一个转换为一个或多个32位的序列来执行16位固定长度指令集架构 说明。 32位指令集架构包括“准备分支”指令，允许在分支之前设置分支指令的目标地址。 组合32位准备到分支和分支指令以执行与16位延迟时隙指令相结合的16位分支指令。

公开(公告)号：US06374348B1

公开(公告)日：2002-04-16

申请号：US09690340

申请日：2000-10-17

申请人： Naohiko Irie ,  Tony Lee Werner

发明人： Naohiko Irie ,  Tony Lee Werner

IPC分类号： G06F938

CPC分类号： G06F9/3804 ,  G06F9/30058 ,  G06F9/322 ,  G06F9/3842 ,  G06F9/3846 ,  G06F9/3885

摘要： An improved preload/prefetching architecture is disclosed for controlling branch target instruction loading in a pipelined processor. Branch target instructions can be speculatively preloaded/prefetched based on a first prediction indicator provided in a branch control instruction, and they also can be actually loaded/fetched based on a second prediction indicator provided in a branch instruction. This mechanism results in reduced cache latency during program execution. The preloading/prefetching of branch target instructions can also be prioritized under software control to optimize instruction execution, based on particular indicators specified for branch target instructions within a branch hint buffer.

摘要翻译： 公开了改进的预加载/预取架构来控制流水线处理器中的分支目标指令加载。 分支目标指令可以基于分支控制指令中提供的第一预测指示符来推测性预加载/预取，并且还可以基于分支指令中提供的第二预测指示符来实际加载/取出分支目标指令。 这种机制导致程序执行期间的缓存延迟减少。 分支目标指令的预加载/预取也可以在软件控制下进行优先级排序，以根据为分支提示缓冲区内的分支目标指令指定的特定指标优化指令执行。