公开(公告)号：US5688717A

公开(公告)日：1997-11-18

申请号：US565308

申请日：1995-11-30

Applicant: Lewis Shen ,  Sheshadri Ramaswami ,  Mark Chang ,  Robin Cheung

Inventor： Lewis Shen ,  Sheshadri Ramaswami ,  Mark Chang ,  Robin Cheung

IPC: H01L23/52 ,  H01L21/3205 ,  H01L23/532 ,  H01L21/28

CPC classification number: H01L23/53223 ,  H01L2924/0002 ,  Y10S257/915

Abstract: A Ti.sub.x N.sub.y layer, not necessarily stoichiometric, is interposed between a titanium or aluminum interconnect layer to improve adhesion and prevent re-entrant undercutting and lifting of the interconnect layer during the process of patterning and plasma etching to form interconnect lines on a substrate, such as an oxide.

公开(公告)号：US5646448A

公开(公告)日：1997-07-08

申请号：US699821

申请日：1996-08-19

Applicant: Richard K. Klein ,  Darrell Erb ,  Steven Avanzino ,  Robin Cheung ,  Scott Luning ,  Bryan Tracy ,  Subhash Gupta ,  Ming-Ren Lin

Inventor： Richard K. Klein ,  Darrell Erb ,  Steven Avanzino ,  Robin Cheung ,  Scott Luning ,  Bryan Tracy ,  Subhash Gupta ,  Ming-Ren Lin

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76805 ,  H01L21/76877 ,  Y10S257/915 ,  Y10S438/927

Abstract: A multilayer semiconductor structure includes a conductive via. The conductive via includes a pellet of metal having a high resistance to electromigration. The pellet is made from a conformal layer of copper or gold deposited over the via to form a copper or gold reservoir or contact located in the via. A barrier layer is provided between the reservoir and an insulating layer to prevent the pellet from diffusing into the insulating layer. The pellet can be formed by selective deposition or by etching a conformal layer. The conformal layer can be deposited by sputtering, collimated sputtering, chemical vapor deposition (CVD), dipping, evaporating, or by other means. The barrier layer and pellet may be etched by anisotropic dry etching, plasma-assisted etching, or other layer removal techniques.

Abstract translation: 多层半导体结构包括导电通孔。 导电通孔包括具有高抗电迁移性的金属颗粒。 沉淀物由沉积在通孔上的铜或金的保形层制成，以形成位于通孔中的铜或金储存器或触点。 在储存器和绝缘层之间设置阻挡层以防止颗粒扩散到绝缘层中。 颗粒可以通过选择性沉积或通过蚀刻保形层形成。 可以通过溅射，准直溅射，化学气相沉积（CVD），浸渍，蒸发或其它方式沉积共形层。 可以通过各向异性干蚀刻，等离子体辅助蚀刻或其它层去除技术来蚀刻阻挡层和颗粒。

公开(公告)号：US5635423A

公开(公告)日：1997-06-03

申请号：US320516

申请日：1994-10-11

Applicant: Richard J. Huang ,  Angela Hui ,  Robin Cheung ,  Mark Chang ,  Ming-Ren Lin

Inventor： Richard J. Huang ,  Angela Hui ,  Robin Cheung ,  Mark Chang ,  Ming-Ren Lin

IPC: H01L21/768 ,  H01L21/44

CPC classification number: H01L21/7681 ,  H01L21/76807 ,  H01L21/76813

Abstract: A semiconductor device containing an interconnection structure having a reduced interwiring spacing is produced by a modified dual damascene process. In one embodiment, an opening for a via is initially formed in a second insulative layer above a first insulative layer with an etch stop layer therebetween. A larger opening for a trench is then formed in the second insulative layer while simultaneously extending the via opening through the etch stop layer and first insulative layer. The trench and via are then simultaneously filled with conductive material.

Abstract translation: 通过改进的双镶嵌工艺产生包含具有减小的布线间距的互连结构的半导体器件。 在一个实施例中，用于通孔的开口最初形成在第一绝缘层之上的第二绝缘层中，其间具有蚀刻停止层。 然后在第二绝缘层中形成用于沟槽的较大开口，同时使通孔开口延伸穿过蚀刻停止层和第一绝缘层。 沟槽和通孔然后同时填充导电材料。