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公开(公告)号：US20190356336A1
公开(公告)日：2019-11-21
申请号：US16530723
申请日：2019-08-02
Inventor： Sung-Ik PARK , Heung-Mook KIM , Sun-Hyoung KWON , Nam-Ho HUR
Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 2/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
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公开(公告)号：US20190334551A1
公开(公告)日：2019-10-31
申请号：US16506486
申请日：2019-07-09
Inventor： Sung-Ik PARK , Sun-Hyoung KWON , Jae-Young LEE , Heung-Mook KIM , Nam-Ho HUR
Abstract: A modulator and a modulation method using a non-uniform 16-symbol signal constellation are disclosed. The modulator includes a memory and a processor. The memory receives a codeword corresponding to a low-density parity check (LDPC) code having a code rate of 3/15. The processor maps the codeword to 16 symbols of the non-uniform 16-symbol signal constellation on a 4-bit basis.
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73.发明申请公开(公告)号：US20190327445A1
公开(公告)日：2019-10-24
申请号：US16460773
申请日：2019-07-02
Inventor： Jae-Young LEE , Sung-Ik PARK , Sun-Hyoung KWON , Heung-Mook KIM
IPC: H04N7/081 , H04N21/2383 , H04N21/2343 , H04N19/187 , H04N3/28 , H04N5/445 , H04L27/26 , H04L1/00 , H04H20/42 , H04N21/236
Abstract: An apparatus and method for broadcast signal frame using layered division multiplexing are disclosed. An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes a combiner configured to generate a multiplexed signal by combining a core layer signal and an enhanced layer signal at different power levels; a power normalizer configured to reduce the power of the multiplexed signal to a power level corresponding to the core layer signal; a time interleaver configured to generate a time-interleaved signal by performing interleaving that is applied to both the core layer signal and the enhanced layer signal; and a frame builder configured to generate a broadcast signal frame including a preamble for signaling, size information of Physical Layer Pipes (PLPs) and time interleaver information shared by the core layer signal and the enhanced layer signal.
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公开(公告)号：US20190327121A1
公开(公告)日：2019-10-24
申请号：US16460189
申请日：2019-07-02
Inventor： Jae-Young LEE , Sun-Hyoung KWON , Sung-Ik PARK , Bo-Mi LIM , Heung-Mook KIM
Abstract: An apparatus and method for generating a broadcast signal frame corresponding to a time interleaver supporting a plurality of operation modes are disclosed. An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes a combiner configured to generate a multiplexed signal by combining a core layer signal and an enhanced layer signal at different power levels; a power normalizer configured to reduce the power of the multiplexed signal to a power level corresponding to the core layer signal; a time interleaver configured to generate a time-interleaved signal by performing interleaving that is applied to both the core layer signal and the enhanced layer signal; and a frame builder configured to generate a broadcast signal frame including a preamble for signaling time interleaver information corresponding to the time interleaver, the time interleaver uses one of time interleaver groups, and the time interleaver performs the interleaving by using one of a plurality of operation modes.
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75.发明申请公开(公告)号：US20190253079A1
公开(公告)日：2019-08-15
申请号：US16395901
申请日：2019-04-26
Inventor： Sung-Ik PARK , Sun-Hyoung KWON , Jae-Young LEE , Heung-Mook KIM
Abstract: A parity interleaving apparatus and method for variable length signaling information are disclosed. A parity interleaving apparatus according to an embodiment of the present invention includes a processor configured to generate a parity bit string for parity puncturing by segmenting parity bits of an LDPC codeword whose length is 16200 and whose code rate is 3/15, into a plurality of groups, and group-wise interleaving the groups using an order of group-wise interleaving; and memory configured to provide the parity bit string for parity puncturing to a parity puncturing unit.
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Patent Agency Ranking
76.发明申请公开(公告)号：US20190181897A1
公开(公告)日：2019-06-13
申请号：US16152849
申请日：2018-10-05
Inventor： Myung-Sun BAEK , Joon-Young JUNG , Heung-Mook KIM
IPC: H04B1/10 , H04B1/04 , H04B17/345 , H04L5/14
Abstract: Disclosed herein are a method for estimating a self-interference signal based on iterative estimation and an apparatus for the same. The method is configured to transmit two preamble signals from the transmission antenna of one terminal to the reception antenna thereof, to estimate third-order nonlinear distortion, which distorts a self-interference signal, based on a transmission signal and a reception signal for each of the two preamble signals, to update the reception signal by eliminating the third-order nonlinear distortion therefrom, to re-estimate the third-order nonlinear distortion based on the updated reception signal, and to estimate the self-interference signal based on the final third-order nonlinear distortion, which is acquired by repeatedly re-estimating the third-order nonlinear distortion as many times as a preset number of iterations.
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公开(公告)号：US20190173487A1
公开(公告)日：2019-06-06
申请号：US16208732
申请日：2018-12-04
Inventor： Eun-Hee HYUN , Je-Won LEE , Heung-Mook KIM , Joon-Young JUNG , Tae-Kyoon KIM
CPC classification number: H03M7/3062 , H03M7/30 , H03M7/3066 , H03M7/3082 , H04L27/364 , H04L27/3854
Abstract: Disclosed herein are a method for transmitting and receiving compressed data and an apparatus therefor. According to the method for transmitting compressed data, a transmission apparatus for transmitting compressed data standardizes the value of an In-phase/Quadrature-phase (IQ) data sample to a preset type that is selected from among a positive number and a negative number, determines the sample type of the IQ data sample, the value of which is standardized to the preset type, based on a sample type determination rule, generates a compressed bit string based on the compression rule pertaining to the determined sample type, generates compressed data, including at least one of a reference bit corresponding to the sample type, the sign bit of the IQ data sample, and the compressed bit string, for each IQ data sample, and transmits the compressed data to a reception apparatus.
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78.发明申请公开(公告)号：US20190150145A1
公开(公告)日：2019-05-16
申请号：US16243831
申请日：2019-01-09
Inventor： Jae-Young LEE , Sung-Ik PARK , Sun-Hyoung KWON , Heung-Mook KIM , Nam-Ho HUR
IPC: H04W72/04 , H04W52/04 , H04L29/06 , H04L5/22 , H04L1/00 , H04W52/34 , H04L27/34 , H04L27/26 , H04J11/00
Abstract: An apparatus and method for broadcast signal frame using layered division multiplexing are disclosed. An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes a combiner configured to generate a multiplexed signal by combining a core layer signal and an enhanced layer signal at different power levels; a power normalizer configured to reduce the power of the multiplexed signal to a power level corresponding to the core layer signal; a time interleaver configured to generate a time-interleaved signal by performing interleaving that is applied to both the core layer signal and the enhanced layer signal; and a frame builder configured to generate a broadcast signal frame including a bootstrap and a preamble using the time-interleaved signal.
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公开(公告)号：US20190097660A1
公开(公告)日：2019-03-28
申请号：US16202519
申请日：2018-11-28
Inventor： Sung-Ik PARK , Sun-Hyoung KWON , Jae-Young LEE , Heung-Mook KIM , Nam-Ho HUR
Abstract: A bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 5/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.
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公开(公告)号：US20190097658A1
公开(公告)日：2019-03-28
申请号：US16200492
申请日：2018-11-26
Inventor： Sung-Ik PARK , Heung-Mook KIM , Sun-Hyoung KWON , Nam-Ho HUR
CPC classification number: H03M13/1177 , H03M13/1102 , H03M13/1105 , H03M13/116 , H03M13/1165 , H03M13/1185 , H03M13/255 , H03M13/616 , H03M13/6552 , H04L1/0057
Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 2/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
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