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71.发明申请公开(公告)号：US20090003594A1
公开(公告)日：2009-01-01
申请号：US11772165
申请日：2007-06-30
申请人： Erdinc Ozturk , Vinodh Gopal , Gilbert Wolrich , Wajdi K. Feghali
发明人： Erdinc Ozturk , Vinodh Gopal , Gilbert Wolrich , Wajdi K. Feghali
CPC分类号： G06F7/72 , G06F5/01 , G06F7/723 , G06F7/725 , H04L9/3066
摘要： Modulus scaling applied a reduction techniques decreases time to perform modular arithmetic operations by avoiding shifting and multiplication operations. Modulus scaling may be applied to both integer and binary fields and the scaling multiplier factor is chosen based on a selected reduction technique for the modular arithmetic operation.
摘要翻译： 使用缩减技术的模量缩放通过避免移位和乘法运算来减少执行模数运算的时间。 可以将模量缩放应用于整数和二进制字段，并且基于用于模数运算的选定的缩减技术来选择缩放倍数因子。
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72.发明申请公开(公告)号：US20090003593A1
公开(公告)日：2009-01-01
申请号：US11772163
申请日：2007-06-30
申请人： Vinodh Gopal , Erdinc Ozturk , Gilbert Wolrich , Wajdi K. Feghali
发明人： Vinodh Gopal , Erdinc Ozturk , Gilbert Wolrich , Wajdi K. Feghali
CPC分类号： H04L9/3066 , G06F7/5324 , G06F7/725
摘要： A system for performing public key encryption is provided. The system supports mathematical operations for a plurality of public key encryption algorithms such as Rivert, Shamir, Aldeman (RSA) and Diffie-Hellman key exchange (DH) and Elliptic Curve Cryptosystem (ECC). The system supports both prime fields and different composite binary fields.
摘要翻译： 提供了一种执行公钥加密的系统。 该系统支持诸如Rivert，Shamir，Aldeman（RSA）和Diffie-Hellman密钥交换（DH）和椭圆曲线加密系统（ECC）的多个公共密钥加密算法的数学运算。 系统支持主域和不同的复合二进制域。
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公开(公告)号：US20140019694A1
公开(公告)日：2014-01-16
申请号：US13631763
申请日：2012-09-28
申请人： Sean M. Gulley , Wajdi K. Feghali , Vinodh Gopal , James D. Guilford , Gilbert Wolrich , Kirk S. Yap
发明人： Sean M. Gulley , Wajdi K. Feghali , Vinodh Gopal , James D. Guilford , Gilbert Wolrich , Kirk S. Yap
IPC分类号： G06F12/00
CPC分类号： G06F5/06 , G06F21/64 , H04L9/0643 , H04L9/3236 , H04L2209/12 , H04L2209/20
摘要： Technologies for executing a serial data processing algorithm on a single variable-length data buffer includes padding data segments of the buffer, streaming the data segments into a data register and executing the serial data processing algorithm on each of the segments in parallel.
摘要翻译： 用于在单个可变长度数据缓冲器上执行串行数据处理算法的技术包括缓冲器的填充数据段，将数据段流传输到数据寄存器中，并且并行地对每个段执行串行数据处理算法。
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公开(公告)号：US09990201B2
公开(公告)日：2018-06-05
申请号：US12645383
申请日：2009-12-22
申请人： Vinodh Gopal , James D. Guilford , Wajdi K. Feghali , Erdine Ozturk , Gilbert M. Wolrich , Martin G. Dixon , Mark C. Davis , Sean P. Mirkes , Alexandre Farcy , Bret L. Toll , Maxim Loktyukhin
发明人： Vinodh Gopal , James D. Guilford , Wajdi K. Feghali , Erdine Ozturk , Gilbert M. Wolrich , Martin G. Dixon , Mark C. Davis , Sean P. Mirkes , Alexandre Farcy , Bret L. Toll , Maxim Loktyukhin
CPC分类号： G06F9/30094 , G06F9/30014
摘要： A method in one aspect may include receiving a multiply instruction. The multiply instruction may indicate a first source operand and a second source operand. A product of the first and second source operands may be stored in one or more destination operands indicated by the multiply instruction. Execution of the multiply instruction may complete without writing a carry flag. Other methods are also disclosed, as are apparatus, systems, and instructions on machine-readable medium.
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公开(公告)号：US20090164543A1
公开(公告)日：2009-06-25
申请号：US11963833
申请日：2007-12-23
IPC分类号： G06F7/483
CPC分类号： G06F7/4873
摘要： A method and apparatus for reducing memory required to store reciprocal approximations as specified in Institute of Electrical and Electronic Engineers (IEEE) standards such as IEEE 754 is presented. Monotonic properties of the reciprocal function are used to bound groups of values. Efficient bit-vectors are used to represent information in groups resulting in a very compact table representation about four times smaller than storing all of the reciprocal approximations in a table.
摘要翻译： 提出了一种用于减少存储相对近似值所需的存储器的方法和装置，如IEEE电气和电子工程师协会（IEEE）标准如IEEE 754所规定。 互逆函数的单调属性用于约束值组。 有效的比特向量用于表示组中的信息，导致非常紧凑的表格表示比存储表中的所有倒数近似的四倍小。
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公开(公告)号：US09270698B2
公开(公告)日：2016-02-23
申请号：US12346734
申请日：2008-12-30
CPC分类号： H04L63/145 , G06F7/02 , G06F17/30949 , G06F17/30985 , G06F21/567 , G06F2207/025 , H04L63/0245 , H04L63/1416
摘要： Methods and apparatus to perform string matching for network packet inspection are disclosed. In some embodiments there is a set of string matching slice circuits, each slice circuit of the set being configured to perform string matching steps in parallel with other slice circuits. Each slice circuit may include an input window storing some number of bytes of data from an input data steam. The input window of data may be padded if necessary, and then multiplied by a polynomial modulo an irreducible Galois-field polynomial to generate a hash index. A storage location of a memory corresponding to the hash index may be accessed to generate a slice-hit signal of a set of H slice-hit signals. The slice-hit signal may be provided to an AND-OR logic array where the set of H slice-hit signals is logically combined into a match result.
摘要翻译： 公开了对网络包检测进行字符串匹配的方法和装置。 在一些实施例中，存在一组字符串匹配限幅电路，该组的每个片电路被配置为与其他片电路并行地执行字符串匹配步骤。 每个切片电路可以包括从输入数据蒸汽存储一些数量的数据字节的输入窗口。 如果需要，可以填充数据的输入窗口，然后乘以多项式模数不可约伽罗瓦域多项式以生成散列索引。 可以访问与散列索引相对应的存储器的存储位置，以产生一组H个切片命中信号的切片命中信号。 切片命中信号可以被提供给AND逻辑阵列，其中H组切片命中信号的组合被逻辑地组合成匹配结果。
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公开(公告)号：US20090019342A1
公开(公告)日：2009-01-15
申请号：US11777538
申请日：2007-07-13
IPC分类号： H03M13/15
CPC分类号： H03M13/091
摘要： A technique of determining a message residue includes accessing a message and simultaneously determining a set of modular remainders with respect to a polynomial for different respective segments of the message. The technique also includes determining a modular remainder with respect to the polynomial for the message based on the set of modular remainders and a set of constants determined prior to accessing the message. The modular remainder with respect to the polynomial for the message is stored in a memory.
摘要翻译： 确定消息残差的技术包括访问消息并且同时确定关于消息的不同相应段的多项式的一组模块余数。 该技术还包括基于模块余数的集合和在访问消息之前确定的一组常数来确定关于消息的多项式的模块余数。 相对于消息的多项式的模数余数存储在存储器中。
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78.发明授权公开(公告)号：US09747105B2
公开(公告)日：2017-08-29
申请号：US12653704
申请日：2009-12-17
申请人： Vinodh Gopal , James D. Guilford , Erdine Ozturk , Wajdi K. Feghali , Gilbert M. Wolrich , Martin G. Dixon
发明人： Vinodh Gopal , James D. Guilford , Erdine Ozturk , Wajdi K. Feghali , Gilbert M. Wolrich , Martin G. Dixon
CPC分类号： G06F9/30145 , G06F9/3001 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/30167 , G06F9/3816 , G06F9/3893
摘要： Method and apparatus for performing a shift and XOR operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources perform a shift and XOR on at least one value.
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公开(公告)号：US08301680B2
公开(公告)日：2012-10-30
申请号：US11963833
申请日：2007-12-23
CPC分类号： G06F7/4873
摘要： A method and apparatus for reducing memory required to store reciprocal approximations as specified in Institute of Electrical and Electronic Engineers (IEEE) standards such as IEEE 754 is presented. Monotonic properties of the reciprocal function are used to bound groups of values. Efficient bit-vectors are used to represent information in groups resulting in a very compact table representation about four times smaller than storing all of the reciprocal approximations in a table.
摘要翻译： 提出了一种用于减少存储相对近似值所需的存储器的方法和装置，如IEEE电气和电子工程师协会（IEEE）标准如IEEE 754所规定。 互逆函数的单调属性用于约束值组。 有效的比特向量用于表示组中的信息，导致非常紧凑的表格表示比存储表中的所有倒数近似的四倍小。
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80.发明申请Method and apparatus for performing a shift and exclusive or operation in a single instruction 有权用于在单个指令中执行移位和排除或操作的方法和装置公开(公告)号：US20110153700A1
公开(公告)日：2011-06-23
申请号：US12653704
申请日：2009-12-17
申请人： Vinodh Gopal , James D. Guilford , Erdine Ozturk , Wajdi K. Feghali , Gilbert M. Wolrich , Martin G. Dixon
发明人： Vinodh Gopal , James D. Guilford , Erdine Ozturk , Wajdi K. Feghali , Gilbert M. Wolrich , Martin G. Dixon
IPC分类号： G06F5/01
CPC分类号： G06F9/30145 , G06F9/3001 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/30167 , G06F9/3816 , G06F9/3893
摘要： Method and apparatus for performing a shift and XOR operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources perform a shift and XOR on at least one value.
摘要翻译： 执行换档和异或运算的方法和装置。 在一个实施例中，一种装置包括执行第一指令的执行资源。 响应于第一指令，所述执行资源对至少一个值执行移位和异或。
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