公开(公告)号：US11599601B2

公开(公告)日：2023-03-07

申请号：US17210293

申请日：2021-03-23

Applicant: Google LLC

Inventor： Andrew Everett Phelps ,  Norman Paul Jouppi

IPC: G06F17/16 ,  G06F15/80 ,  G06F5/01 ,  G06F9/30 ,  G06N3/04 ,  G06N3/08

Abstract: Methods, systems, and apparatus for a matrix multiply unit implemented as a systolic array of cells are disclosed. Each cell of the matrix multiply includes: a weight matrix register configured to receive a weight input from either a transposed or a non-transposed weight shift register; a transposed weight shift register configured to receive a weight input from a horizontal direction to be stored in the weight matrix register; a non-transposed weight shift register configured to receive a weight input from a vertical direction to be stored in the weight matrix register; and a multiply unit that is coupled to the weight matrix register and configured to multiply the weight input of the weight matrix register with a vector data input in order to obtain a multiplication result.

公开(公告)号：US11321273B2

公开(公告)日：2022-05-03

申请号：US17037286

申请日：2020-09-29

Applicant: Google LLC

Inventor： Kyle Nesbit ,  Andrew Everett Phelps

IPC: G06F15/173 ,  G06F3/06

Abstract: A distributed storage system including memory hosts and at least one curator in communication with the memory hosts. Each memory host has memory, and the curator manages striping of data across the memory hosts. In response to a memory access request by a client in communication with the memory hosts and the curator, the curator provides the client a file descriptor mapping data stripes and data stripe replications of a file on the memory hosts for remote direct memory access of the file on the memory hosts.

公开(公告)号：US20210318983A1

公开(公告)日：2021-10-14

申请号：US17354947

申请日：2021-06-22

Applicant: Google LLC

Inventor： Gregory Michael Thorson ,  Andrew Everett Phelps ,  Olivier Temam

IPC: G06F15/80 ,  G06F9/30 ,  G06F17/16 ,  G06F9/38

Abstract: A vector reduction circuit configured to reduce an input vector of elements comprises a plurality of cells, wherein each of the plurality of cells other than a designated first cell that receives a designated first element of the input vector is configured to receive a particular element of the input vector, receive, from another of the one or more cells, a temporary reduction element, perform a reduction operation using the particular element and the temporary reduction element, and provide, as a new temporary reduction element, a result of performing the reduction operation using the particular element and the temporary reduction element. The vector reduction circuit also comprises an output circuit configured to provide, for output as a reduction of the input vector, a new temporary reduction element corresponding to a result of performing the reduction operation using a last element of the input vector.

公开(公告)号：US20210263739A1

公开(公告)日：2021-08-26

申请号：US17007569

申请日：2020-08-31

Applicant: Google LLC

Inventor： Thomas Norrie ,  Gurushankar Rajamani ,  Andrew Everett Phelps ,  Matthew Leever Hedlund ,  Norman Paul Jouppi

IPC: G06F9/30 ,  G06F13/28 ,  G06N3/04

Abstract: Methods, systems, and apparatus, including computer-readable media, are described for performing vector reductions using a shared scratchpad memory of a hardware circuit having processor cores that communicate with the shared memory. For each of the processor cores, a respective vector of values is generated based on computations performed at the processor core. The shared memory receives the respective vectors of values from respective resources of the processor cores using a direct memory access (DMA) data path of the shared memory. The shared memory performs an accumulation operation on the respective vectors of values using an operator unit coupled to the shared memory. The operator unit is configured to accumulate values based on arithmetic operations encoded at the operator unit. A result vector is generated based on performing the accumulation operation using the respective vectors of values.

公开(公告)号：US20210232898A1

公开(公告)日：2021-07-29

申请号：US15931970

申请日：2020-05-14

Applicant: Google LLC

Inventor： Thomas Norrie ,  Andrew Everett Phelps ,  Norman Paul Jouppi ,  Matthew Leever Hedlund

IPC: G06N3/063 ,  G06F9/54 ,  G06F13/16 ,  G06F15/80 ,  G06F17/16

Abstract: Methods, systems, and apparatus, including computer-readable media, are described for a hardware circuit configured to implement a neural network. The circuit includes a first memory, respective first and second processor cores, and a shared memory. The first memory provides data for performing computations to generate an output for a neural network layer. Each of the first and second cores include a vector memory for storing vector values derived from the data provided by the first memory. The shared memory is disposed generally intermediate the first memory and at least one core and includes: i) a direct memory access (DMA) data path configured to route data between the shared memory and the respective vector memories of the first and second cores and ii) a load-store data path configured to route data between the shared memory and respective vector registers of the first and second cores.

公开(公告)号：US11061854B2

公开(公告)日：2021-07-13

申请号：US16918448

申请日：2020-07-01

Applicant: Google LLC

Inventor： Gregory Michael Thorson ,  Andrew Everett Phelps ,  Olivier Temam

IPC: G06F15/80 ,  G06F9/30 ,  G06F17/16 ,  G06F9/38 ,  G06N3/08

Abstract: A vector reduction circuit configured to reduce an input vector of elements comprises a plurality of cells, wherein each of the plurality of cells other than a designated first cell that receives a designated first element of the input vector is configured to receive a particular element of the input vector, receive, from another of the one or more cells, a temporary reduction element, perform a reduction operation using the particular element and the temporary reduction element, and provide, as a new temporary reduction element, a result of performing the reduction operation using the particular element and the temporary reduction element. The vector reduction circuit also comprises an output circuit configured to provide, for output as a reduction of the input vector, a new temporary reduction element corresponding to a result of performing the reduction operation using a last element of the input vector.

公开(公告)号：US11016764B2

公开(公告)日：2021-05-25

申请号：US16843015

申请日：2020-04-08

Applicant: Google LLC

Inventor： William Lacy ,  Gregory Michael Thorson ,  Christopher Aaron Clark ,  Norman Paul Jouppi ,  Thomas Norrie ,  Andrew Everett Phelps

IPC: G06F9/302 ,  G06F9/312 ,  G06F15/80 ,  G06F13/40 ,  G06F7/57 ,  G06N3/063 ,  G06N20/00 ,  G06F17/16 ,  G06F9/30 ,  G06F9/38 ,  G06F7/58 ,  G06F13/36 ,  G06F13/42

Abstract: A vector processing unit is described, and includes processor units that each include multiple processing resources. The processor units are each configured to perform arithmetic operations associated with vectorized computations. The vector processing unit includes a vector memory in data communication with each of the processor units and their respective processing resources. The vector memory includes memory banks configured to store data used by each of the processor units to perform the arithmetic operations. The processor units and the vector memory are tightly coupled within an area of the vector processing unit such that data communications are exchanged at a high bandwidth based on the placement of respective processor units relative to one another, and based on the placement of the vector memory relative to each processor unit.

公开(公告)号：US20200371748A1

公开(公告)日：2020-11-26

申请号：US16719954

申请日：2019-12-18

Applicant: Google LLC

Inventor： Hsin-Jung Yang ,  Andrew Everett Phelps

IPC: G06F7/499 ,  G06F7/485 ,  G06F9/30

Abstract: Methods, systems, and apparatus, including an apparatus for adding three or more floating-point numbers. In one aspect, a method includes receiving, for each of three or more operands, a set of bits that include a floating-point representation of the operand. A given operand is identified. For each other operand, the mantissa bits of the operand are shifted such that the bits of the operand align with the bits of the given operand. A sticky bit for each other operand is determined. An overall sticky bit value is determined based on each sticky bit. The overall sticky bit value is zero whenever all of the sticky bits are zero or at least two sticky bits are non-zero and do not match. The overall sticky bit value matches the value of each non-zero sticky bit whenever all of the non-zero sticky bits match or there is only one non-zero sticky bit.

公开(公告)号：US10831862B2

公开(公告)日：2020-11-10

申请号：US16826075

申请日：2020-03-20

Applicant: Google LLC

Inventor： Andrew Everett Phelps ,  Norman Paul Jouppi

IPC: G06F17/16 ,  G06N3/02 ,  G06F7/487 ,  G06N3/063 ,  G06F9/30 ,  G06N3/04 ,  G06F7/483

Abstract: Methods, systems, and apparatus for performing a matrix multiplication using a hardware circuit are described. An example method begins by obtaining an input activation value and a weight input value in a first floating point format. The input activation value and the weight input value are multiplied to generate a product value in a second floating point format that has higher precision than the first floating point format. A partial sum value is obtained in a third floating point format that has a higher precision than the first floating point format. The partial sum value and the product value are combined to generate an updated partial sum value that has the third floating point format.

公开(公告)号：US20200334198A1

公开(公告)日：2020-10-22

申请号：US16918448

申请日：2020-07-01

Applicant: Google LLC

Inventor： Gregory Michael Thorson ,  Andrew Everett Phelps ,  Olivier Temam

IPC: G06F15/80 ,  G06F9/30 ,  G06F17/16 ,  G06F9/38

Abstract: A vector reduction circuit configured to reduce an input vector of elements comprises a plurality of cells, wherein each of the plurality of cells other than a designated first cell that receives a designated first element of the input vector is configured to receive a particular element of the input vector, receive, from another of the one or more cells, a temporary reduction element, perform a reduction operation using the particular element and the temporary reduction element, and provide, as a new temporary reduction element, a result of performing the reduction operation using the particular element and the temporary reduction element. The vector reduction circuit also comprises an output circuit configured to provide, for output as a reduction of the input vector, a new temporary reduction element corresponding to a result of performing the reduction operation using a last element of the input vector.