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    Dispersion reduced dielectric waveguide comprising dielectric materials having respective dispersion responses
    71.
    发明授权
    Dispersion reduced dielectric waveguide comprising dielectric materials having respective dispersion responses 有权

    公开(公告)号：US11165129B2

    公开(公告)日：2021-11-02

    申请号：US16463329

    申请日：2016-12-30

    Applicant: Intel Corporation

    Inventor： Georgios Dogiamis ,  Sasha Oster ,  Telesphor Kamgaing

    IPC: H01P3/16 ,  H01P3/12 ,  H01P11/00 ,  H01P5/08

    Abstract: Embodiments of the invention include a dispersion reduced dielectric waveguide and methods of forming such devices. In an embodiment, the dispersion reduced dielectric waveguide may include a first dielectric material that has a first Dk-value, and a second dielectric material that has a second Dk-value that is greater than the first Dk-value. In an embodiment, the dispersion reduced dielectric waveguide may also include a conductive layer formed around the first and second dielectric materials. According to an embodiment, a first portion of a bandwidth of a signal that is propagated along the dispersion reduced dielectric waveguide is primarily propagated along the first dielectric material, and a second portion of a bandwidth of the signal that is propagated along the dispersion reduced dielectric waveguide is primarily propagated along the second dielectric material.

    INORGANIC DIES WITH ORGANIC INTERCONNECT LAYERS AND RELATED STRUCTURES
    73.
    发明申请
    INORGANIC DIES WITH ORGANIC INTERCONNECT LAYERS AND RELATED STRUCTURES 有权

    公开(公告)号：US20210296175A1

    公开(公告)日：2021-09-23

    申请号：US17338296

    申请日：2021-06-03

    Applicant: Intel Corporation

    Inventor： Aleksandar Aleksov ,  Feras Eid ,  Telesphor Kamgaing ,  Georgios Dogiamis ,  Johanna M. Swan

    IPC: H01L21/768 ,  H01L23/00

    Abstract: Disclosed herein are methods to fabricate inorganic dies with organic interconnect layers and related structures and devices. In some embodiments, an integrated circuit (IC) structure may be formed to include an inorganic die and one or more organic interconnect layers on the inorganic die, wherein the organic interconnect layers include an organic dielectric. An example method includes forming organic interconnect layers over an inorganic interconnect substrate and forming passive components in the organic interconnect layer. The organic interconnect layers comprise a plurality of conductive metal layers through an organic dielectric material. The plurality of conductive metal layers comprises electrical pathways. the passive components are electrically coupled to the electrical pathways.

    MICROELECTRONIC PACKAGE WITH MOLD-INTEGRATED COMPONENTS
    74.
    发明申请
    MICROELECTRONIC PACKAGE WITH MOLD-INTEGRATED COMPONENTS 有权

    公开(公告)号：US20210233856A1

    公开(公告)日：2021-07-29

    申请号：US17229991

    申请日：2021-04-14

    Applicant: Intel Corporation

    Inventor： Georgios Dogiamis ,  Aleksandar Aleksov ,  Feras Eid ,  Telesphor Kamgaing ,  Johanna M. Swan

    IPC: H01L23/538 ,  B81B7/00 ,  H01L23/28 ,  H01L23/552 ,  H01L21/56

    Abstract: Embodiments may relate to a microelectronic package that includes an overmold material, a redistribution layer (RDL) in the overmold material, and a die in the overmold material electrically coupled with the RDL on an active side of the die. The RDL is configured to provide electrical interconnection within the overmold material and includes at least one mold interconnect. The microelectronic package may also include a through-mold via (TMV) disposed in the overmold material and electrically coupled to the RDL by the mold interconnect. In some embodiments, the microelectronics package further includes a surface mount device (SMD) in the overmold material. The microelectronics package may also include a substrate having a face on which the overmold is disposed.

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