公开(公告)号：US20220028788A1

公开(公告)日：2022-01-27

申请号：US17492476

申请日：2021-10-01

申请人： Intel Corporation

发明人： Srinivas V. PIETAMBARAM ,  Tarek IBRAHIM ,  Kristof DARMAWIKARTA ,  Rahul N. MANEPALLI ,  Debendra MALLIK ,  Robert L. SANKMAN

IPC分类号： H01L23/538 ,  H01L23/48 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065

摘要： A glass substrate houses an embedded multi-die interconnect bridge that is part of a semiconductor device package. Through-glass vias communicate to a surface for mounting on a semiconductor package substrate.

公开(公告)号：US20210343653A1

公开(公告)日：2021-11-04

申请号：US17374886

申请日：2021-07-13

申请人： Intel Corporation

发明人： Srinivas V. PIETAMBARAM ,  Sri Ranga Sai BOYAPATI ,  Robert A. MAY ,  Kristof DARMAWIKARTA ,  Javier SOTO GONZALEZ ,  Kwangmo LIM

IPC分类号： H01L23/538 ,  H01L23/00

摘要： A foundation layer and methods of forming a conductive via are described. A die pad is formed over a die. A seed layer is deposited over the die pad and the foundation layer. A first photoresist layer is deposited over the seed layer, and the first layer is patterned to form a conductive line opening over the die pad. A conductive material is deposited into the conductive line opening to form a conductive line. A second photoresist layer is deposited over the first layer, and the second layer is patterned to form a via opening over the conductive line. The conductive material is deposited into the via opening to form the conductive via, where the conductive material only deposits on portions of exposed conductive line. The second and first layers are removed. Portions of exposed seed layer are recessed, and then a top surface of the conductive via is exposed.

公开(公告)号：US20210035901A1

公开(公告)日：2021-02-04

申请号：US17075533

申请日：2020-10-20

申请人： Intel Corporation

发明人： Srinivas V. PIETAMBARAM ,  Jung Kyu HAN ,  Ali LEHAF ,  Steve CHO ,  Thomas HEATON ,  Hiroki TANAKA ,  Kristof DARMAWIKARTA ,  Robert Alan MAY ,  Sri Ranga Sai BOYAPATI

IPC分类号： H01L23/498 ,  H01L23/538 ,  H01L25/18 ,  H01L21/48 ,  H01L23/00 ,  H01L25/00

摘要： A package assembly includes a substrate and at least a first die having a first contact array and a second contact array. First and second via assemblies are respectively coupled with the first and second contact arrays. Each of the first and second via assemblies includes a base pad, a cap assembly, and a via therebetween. One or more of the cap assembly or the via includes an electromigration resistant material to isolate each of the base pad and the cap assembly. Each first cap assembly and via of the first via assemblies has a first assembly profile less than a second assembly profile of each second cap assembly and via of the second via assemblies. The first and second cap assemblies have a common applied thickness in an application configuration. The first and second cap assemblies have a thickness variation of ten microns or less in a reflowed configuration.

公开(公告)号：US20200350251A1

公开(公告)日：2020-11-05

申请号：US16931690

申请日：2020-07-17

申请人： Intel Corporation

发明人： Srinivas V. PIETAMBARAM ,  Rahul N. MANEPALLI

IPC分类号： H01L23/538 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065

摘要： Electrical interconnect bridge technology is disclosed. An electrical interconnect bridge can include a bridge substrate formed of a mold compound material. The electrical interconnect bridge can also include a plurality of routing layers within the bridge substrate, each routing layer having a plurality of fine line and space (FLS) traces. In addition, the electrical interconnect bridge can include a via extending through the substrate and electrically coupling at least one of the FLS traces in one of the routing layers to at least one of the FLS traces in another of the routing layers.

公开(公告)号：US20190279935A1

公开(公告)日：2019-09-12

申请号：US16349932

申请日：2016-12-29

申请人： Intel Corporation

发明人： David Allen UNRUH, JR. ,  Srinivas V. PIETAMBARAM ,  Rahul N. MANEPALLI

IPC分类号： H01L23/532 ,  H01L23/522 ,  H01L25/065 ,  H05K1/09 ,  H05K1/18 ,  H01L23/00

摘要： Semiconductor packages including package substrates having non-homogeneous dielectric layers, and methods of fabricating such semiconductor packages, are described. In an example, a semiconductor package substrate includes a dielectric layer having a resin-rich region, e.g., a resin-rich sublayer, and a filler-rich region, e.g., a filler-rich sublayer. The sublayers may contain respective mixtures of an organic resin material and an inorganic filler material. The filler-rich sublayer may have a higher density of the inorganic filler material than the resin-rich sublayer. A density of the inorganic filler material may be lesser near a top surface of 0 the dielectric layer in which an electrical interconnect is embedded. The electrical interconnect may have a greater adhesion affinity to the organic resin material than the inorganic filler material, and thus, the electrical interconnect may readily attach to the functionally-graded dielectric layer.

公开(公告)号：US20190189563A1

公开(公告)日：2019-06-20

申请号：US16326679

申请日：2016-09-29

申请人： Intel Corporation

发明人： Srinivas V. PIETAMBARAM ,  Sri Ranga Sai BOYAPATI ,  Robert A. MAY ,  Kristof DARMAWIKARTA ,  Javier SOTO GONZALEZ ,  Kwangmo LIM

IPC分类号： H01L23/538 ,  H01L23/00

CPC分类号： H01L23/5389 ,  H01L23/00 ,  H01L24/06 ,  H01L2224/04105 ,  H01L2224/18 ,  H01L2224/24137 ,  H01L2924/18162

摘要： A foundation layer and methods of forming a conductive via are described. A die pad is formed over a die. A seed layer is deposited over the die pad and the foundation layer. A first photoresist layer is deposited over the seed layer, and the first layer is patterned to form a conductive line opening over the die pad. A conductive material is deposited into the conductive line opening to form a conductive line. A second photoresist layer is deposited over the first layer, and the second layer is patterned to form a via opening over the conductive line. The conductive material is deposited into the via opening to form the conductive via, where the conductive material only deposits on portions of exposed conductive line. The second and first layers are removed. Portions of exposed seed layer are recessed, and then a top surface of the conductive via is exposed.