公开(公告)号：US20210020532A1

公开(公告)日：2021-01-21

申请号：US16511376

申请日：2019-07-15

Applicant: Intel Corporation

Inventor： Jacob VEHONSKY ,  Nicholas S. HAEHN ,  Thomas HEATON ,  Steve S. CHO ,  Rahul JAIN ,  Tarek IBRAHIM ,  Antariksh Rao Pratap SINGH ,  Edvin CETEGEN ,  Nicholas NEAL ,  Sergio CHAN ARGUEDAS

IPC: H01L23/16 ,  H01L23/498 ,  H01L23/00 ,  H01L23/367

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment an electronic package comprises a package substrate, and a first level interconnect (FLI) bump region on the package substrate. In an embodiment, the FLI bump region comprises a plurality of pads, and a plurality of bumps, where each bump is over a different one of the plurality of pads. In an embodiment, the electronic package further comprises a guard feature adjacent to the FLI bump region. In an embodiment, the guard feature comprises, a guard pad, and a guard bump over the guard pad, wherein the guard feature is electrically isolated from circuitry of the electronic package.

公开(公告)号：US20210020531A1

公开(公告)日：2021-01-21

申请号：US16511360

申请日：2019-07-15

Applicant: Intel Corporation

Inventor： Edvin CETEGEN ,  Jacob VEHONSKY ,  Nicholas S. HAEHN ,  Thomas HEATON ,  Steve S. CHO ,  Rahul JAIN ,  Tarek IBRAHIM ,  Antariksh Rao Pratap SINGH ,  Nicholas NEAL ,  Sergio CHAN ARGUEDAS ,  Vipul MEHTA

IPC: H01L23/16 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065

Abstract: Embodiments disclosed herein include electronic packages with underfill flow control features. In an embodiment, an electronic package comprises a package substrate and a plurality of interconnects on the package substrate. In an embodiment, a die is coupled to the package substrate by the plurality of interconnects and a flow control feature is adjacent on the package substrate. In an embodiment, the flow control feature is electrically isolated from circuitry of the electronic package. In an embodiment, the electronic package further comprises an underfill surrounding the plurality of interconnects and in contact with the flow control feature.

公开(公告)号：US20240258183A1

公开(公告)日：2024-08-01

申请号：US18632047

申请日：2024-04-10

Applicant: Intel Corporation

Inventor： Edvin CETEGEN ,  Jacob VEHONSKY ,  Nicholas S. HAEHN ,  Thomas HEATON ,  Steve S. CHO ,  Rahul JAIN ,  Tarek IBRAHIM ,  Antariksh Rao Pratap SINGH ,  Nicholas NEAL ,  Sergio CHAN ARGUEDAS ,  Vipul MEHTA

IPC: H01L23/16 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/16 ,  H01L23/3185 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2924/18161

Abstract: Embodiments disclosed herein include electronic packages with underfill flow control features. In an embodiment, an electronic package comprises a package substrate and a plurality of interconnects on the package substrate. In an embodiment, a die is coupled to the package substrate by the plurality of interconnects and a flow control feature is adjacent on the package substrate. In an embodiment, the flow control feature is electrically isolated from circuitry of the electronic package. In an embodiment, the electronic package further comprises an underfill surrounding the plurality of interconnects and in contact with the flow control feature.

公开(公告)号：US20210014972A1

公开(公告)日：2021-01-14

申请号：US16505403

申请日：2019-07-08

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Tarek IBRAHIM ,  Srinivas PIETAMBARAM ,  Andrew J. BROWN ,  Gang DUAN ,  Jeremy ECTON ,  Sheng C. LI

IPC: H05K1/16 ,  H01L23/00 ,  H01F27/40 ,  H05K1/11 ,  H05K3/40 ,  H05K3/28

Abstract: Embodiments include package substrates and method of forming the package substrates. A package substrate includes a first encapsulation layer over a substrate, and a second encapsulation layer below the substrate. The package substrate also includes a first interconnect and a second interconnect vertically in the first encapsulation layer, the second encapsulation layer, and the substrate. The first interconnect includes a first plated-through-hole (PTH) core, a first via, and a second via, and the second interconnect includes a second PTH core, a third via, and a fourth via. The package substrate further includes a magnetic portion that vertically surrounds the first interconnect. The first PTH core has a top surface directly coupled to the first via, and a bottom surface directly coupled to the second via. The second PTH core has a top surface directly coupled to the third via, and a bottom surface directly coupled to the fourth via.

公开(公告)号：US20230420375A1

公开(公告)日：2023-12-28

申请号：US18367285

申请日：2023-09-12

Applicant: Intel Corporation

Inventor： Srinivas V. PIETAMBARAM ,  Tarek IBRAHIM ,  Kristof DARMAWIKARTA ,  Rahul N. MANEPALLI ,  Debendra MALLIK ,  Robert L. SANKMAN

IPC: H01L23/538 ,  H01L23/48 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/5383 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49894 ,  H01L24/09 ,  H01L25/0652

Abstract: A glass substrate houses an embedded multi-die interconnect bridge that is part of a semiconductor device package. Through-glass vias communicate to a surface for mounting on a semiconductor package substrate.

公开(公告)号：US20220028788A1

公开(公告)日：2022-01-27

申请号：US17492476

申请日：2021-10-01

Applicant: Intel Corporation

Inventor： Srinivas V. PIETAMBARAM ,  Tarek IBRAHIM ,  Kristof DARMAWIKARTA ,  Rahul N. MANEPALLI ,  Debendra MALLIK ,  Robert L. SANKMAN

IPC: H01L23/538 ,  H01L23/48 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065

Abstract: A glass substrate houses an embedded multi-die interconnect bridge that is part of a semiconductor device package. Through-glass vias communicate to a surface for mounting on a semiconductor package substrate.