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1.发明申请公开(公告)号：US20160095209A1
公开(公告)日：2016-03-31
申请号：US14498958
申请日：2014-09-26
Applicant: Intel Corporation
Inventor： Robert STARKSTON , John GUZEK , Patrick NARDI , Keith JONES , Javier SOTO GONZALEZ
CPC classification number: H05K1/0271 , H01L23/16 , H01L23/49833 , H01L23/562 , H01L24/97 , H01L2224/16225 , H01L2924/15311 , H05K3/0052 , H05K3/0097 , H05K3/284 , H05K2201/09136 , H05K2201/10977 , H05K2201/2009
Abstract: Techniques are disclosed for forming a package substrate with integrated stiffener. A panel of package substrates are provided. An adhesion layer is then formed on each package substrate of the panel of package substrates. A panel of stiffeners are then attached to the panel of package substrates by the adhesion layer, each stiffener corresponding to a respective package substrate. The panel of package substrates is then singulated into individual package substrates with integrated stiffeners. The stiffeners on the singulated package substrates include tabs that extend to the edges of the package substrates.
Abstract translation: 公开了用于形成具有集成的加强件的封装衬底的技术。 提供了一组封装基板。 然后在封装衬底面板的每个封装衬底上形成粘附层。 然后，通过粘合层将一块扶强材板附接到封装基板的面板，每个加强件对应于相应的封装基板。 然后将封装衬底的面板分成具有集成的加强件的单个封装衬底。 单个封装衬底上的加强件包括延伸到封装衬底的边缘的突片。
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公开(公告)号：US20210035818A1
公开(公告)日：2021-02-04
申请号：US16525985
申请日：2019-07-30
Applicant: Intel Corporation
Inventor： Tarek A. IBRAHIM , Rahul N. MANEPALLI , Wei-Lun K. JEN , Steve S. CHO , Jason M. GAMBA , Javier SOTO GONZALEZ
IPC: H01L21/48 , H01L23/538 , H01L23/498
Abstract: Embodiments disclosed herein include electronic packages and methods of making electronic packages. In an embodiment, the electronic package comprises a package substrate, an array of first level interconnect (FLI) bumps on the package substrate, wherein each FLI bump comprises a surface finish, a first pad on the package substrate, wherein the first pad comprises the surface finish, and wherein a first FLI bump of the array of FLI bumps is electrically coupled to the first pad, and a second pad on the package substrate, wherein the second pad is electrically coupled to the first pad.
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公开(公告)号：US20210193583A1
公开(公告)日：2021-06-24
申请号：US17192462
申请日：2021-03-04
Applicant: INTEL CORPORATION
Inventor： Adel A. ELSHERBINI , Johanna M. SWAN , Shawna M. LIFF , Henning BRAUNISCH , Krishna BHARATH , Javier SOTO GONZALEZ , Javier A. FALCON
IPC: H01L23/538 , H01L21/48 , H01L23/00 , H01L25/065 , H01L25/00 , H01L25/03 , H01L23/498
Abstract: Various embodiments disclosed relate to a semiconductor package. The present semiconductor package includes a substrate. The substrate is formed from alternating conducting layers and dielectric layers. A first active electronic component is disposed on an external surface of the substrate, and a second active electronic component is at least partially embedded within the substrate. A first interconnect region is formed from a plurality of interconnects between the first active electronic component and the second active electronic component. Between the first active electronic component and the substrate a second interconnect region is formed from a plurality of interconnects. Additionally, a third interconnect region is formed from a plurality of interconnects between the second active electronic component and the substrate.
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公开(公告)号：US20180315690A1
公开(公告)日：2018-11-01
申请号：US15773030
申请日：2015-12-21
Applicant: Intel Corporation
Inventor： Adel A. ELSHERBINI , Mathew J. MANUSHAROW , Krishna BHARATH , William J. LAMBERT , Robert L. SANKMAN , Aleksandar ALEKSOV , Brandon M. RAWLINGS , Feras EID , Javier SOTO GONZALEZ , Meizi JIAO , Suddhasattwa NAD , Telesphor KAMGAING
CPC classification number: H01F27/40 , H01F17/0006 , H01L28/00
Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, a transformer may be formed in the electrical package. The transformer may include a first conductive loop that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first conductive loop from a second conductive loop that is formed in the package. Additional embodiments of the invention include forming a capacitor formed in the electrical package. For example, the capacitor may include a first capacitor plate that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first capacitor plate form a second capacitor plate that is formed in the package. The thin dielectric spacer material in the transformer and capacitor allow for increased coupling factors and capacitance density in electrical components.
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5.发明申请公开(公告)号：US20150221608A1
公开(公告)日：2015-08-06
申请号：US14686210
申请日：2015-04-14
Applicant: Intel Corporation
IPC: H01L23/00 , H01L23/498
CPC classification number: H01L24/17 , H01L21/4857 , H01L21/486 , H01L23/3128 , H01L23/49811 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L2224/05571 , H01L2224/05573 , H01L2224/16113 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2924/00014 , H01L2924/12042 , H01L2924/14 , H01L2924/1433 , H01L2924/2064 , H01L2924/20642 , H01L2924/20643 , H01L2924/20644 , H05K1/113 , H05K3/0035 , H05K3/007 , H05K3/20 , H05K3/244 , H05K3/28 , H05K3/3457 , H05K3/4007 , H05K3/4682 , H05K2201/0367 , H05K2201/096 , H05K2203/0152 , H05K2203/1536 , Y10T29/49147 , H01L2924/00 , H01L2224/05599
Abstract: A microelectronic device includes a laminated mounting substrate including a die side and a land side with a surface finish layer disposed in a recess on the mounting substrate die side. An electrically conductive first plug is in contact with the surface finish layer and an electrically conductive subsequent plug is disposed on the mounting substrate land side and it is electrically coupled to the electrically conductive first plug and disposed directly below the electrically conductive first plug.
Abstract translation: 微电子器件包括层叠安装基板，其包括裸片侧和具有设置在安装基板裸片侧的凹部中的表面光洁度层的平台侧。 导电的第一插头与表面光洁度层接触，并且导电的后续插头设置在安装衬底接地侧上，并且其电耦合到导电的第一插头并且直接设置在导电的第一插头的正下方。
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Patent Agency Ranking
6.发明公开公开(公告)号：US20230326866A1
公开(公告)日：2023-10-12
申请号：US18208785
申请日：2023-06-12
Applicant: Intel Corporation
Inventor： Srinivas V. PIETAMBARAM , Sri Ranga Sai BOYAPATI , Robert A. MAY , Kristof DARMAWIKARTA , Javier SOTO GONZALEZ , Kwangmo LIM
IPC: H01L23/538 , H01L23/00
CPC classification number: H01L23/5389 , H01L23/00 , H01L24/06 , H01L2224/04105 , H01L2224/24137 , H01L2924/18162 , H01L2224/18
Abstract: A foundation layer and methods of forming a conductive via are described. A die pad is formed over a die. A seed layer is deposited over the die pad and the foundation layer. A first photoresist layer is deposited over the seed layer, and the first layer is patterned to form a conductive line opening over the die pad. A conductive material is deposited into the conductive line opening to form a conductive line. A second photoresist layer is deposited over the first layer, and the second layer is patterned to form a via opening over the conductive line. The conductive material is deposited into the via opening to form the conductive via, where the conductive material only deposits on portions of exposed conductive line. The second and first layers are removed. Portions of exposed seed layer are recessed, and then a top surface of the conductive via is exposed.
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公开(公告)号：US20220102261A1
公开(公告)日：2022-03-31
申请号：US17544693
申请日：2021-12-07
Applicant: Intel Corporation
Inventor： Adel A. ELSHERBINI , Mathew J. MANUSHAROW , Krishna BHARATH , William J. LAMBERT , Robert L. SANKMAN , Aleksandar ALEKSOV , Brandon M. RAWLINGS , Feras EID , Javier SOTO GONZALEZ , Meizi JIAO , Suddhasattwa NAD , Telesphor KAMGAING
IPC: H01L23/498 , H01F17/00 , H01F27/40 , H01L49/02 , H01F27/28 , H01F41/04 , H01G4/33 , H01L21/48 , H01L23/66
Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, a transformer may be formed in the electrical package. The transformer may include a first conductive loop that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first conductive loop from a second conductive loop that is formed in the package. Additional embodiments of the invention include forming a capacitor formed in the electrical package. For example, the capacitor may include a first capacitor plate that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first capacitor plate form a second capacitor plate that is formed in the package. The thin dielectric spacer material in the transformer and capacitor allow for increased coupling factors and capacitance density in electrical components.
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公开(公告)号：US20210343653A1
公开(公告)日：2021-11-04
申请号：US17374886
申请日：2021-07-13
Applicant: Intel Corporation
Inventor： Srinivas V. PIETAMBARAM , Sri Ranga Sai BOYAPATI , Robert A. MAY , Kristof DARMAWIKARTA , Javier SOTO GONZALEZ , Kwangmo LIM
IPC: H01L23/538 , H01L23/00
Abstract: A foundation layer and methods of forming a conductive via are described. A die pad is formed over a die. A seed layer is deposited over the die pad and the foundation layer. A first photoresist layer is deposited over the seed layer, and the first layer is patterned to form a conductive line opening over the die pad. A conductive material is deposited into the conductive line opening to form a conductive line. A second photoresist layer is deposited over the first layer, and the second layer is patterned to form a via opening over the conductive line. The conductive material is deposited into the via opening to form the conductive via, where the conductive material only deposits on portions of exposed conductive line. The second and first layers are removed. Portions of exposed seed layer are recessed, and then a top surface of the conductive via is exposed.
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9.发明申请公开(公告)号：US20190189563A1
公开(公告)日：2019-06-20
申请号：US16326679
申请日：2016-09-29
Applicant: Intel Corporation
Inventor： Srinivas V. PIETAMBARAM , Sri Ranga Sai BOYAPATI , Robert A. MAY , Kristof DARMAWIKARTA , Javier SOTO GONZALEZ , Kwangmo LIM
IPC: H01L23/538 , H01L23/00
CPC classification number: H01L23/5389 , H01L23/00 , H01L24/06 , H01L2224/04105 , H01L2224/18 , H01L2224/24137 , H01L2924/18162
Abstract: A foundation layer and methods of forming a conductive via are described. A die pad is formed over a die. A seed layer is deposited over the die pad and the foundation layer. A first photoresist layer is deposited over the seed layer, and the first layer is patterned to form a conductive line opening over the die pad. A conductive material is deposited into the conductive line opening to form a conductive line. A second photoresist layer is deposited over the first layer, and the second layer is patterned to form a via opening over the conductive line. The conductive material is deposited into the via opening to form the conductive via, where the conductive material only deposits on portions of exposed conductive line. The second and first layers are removed. Portions of exposed seed layer are recessed, and then a top surface of the conductive via is exposed.
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10.发明申请公开(公告)号：US20250125277A1
公开(公告)日：2025-04-17
申请号：US19000025
申请日：2024-12-23
Applicant: Intel Corporation
Inventor： Srinivas V. PIETAMBARAM , Sri Ranga Sai BOYAPATI , Robert A. MAY , Kristof DARMAWIKARTA , Javier SOTO GONZALEZ , Kwangmo LIM
IPC: H01L23/538 , H01L23/00
Abstract: A foundation layer and methods of forming a conductive via are described. A die pad is formed over a die. A seed layer is deposited over the die pad and the foundation layer. A first photoresist layer is deposited over the seed layer, and the first layer is patterned to form a conductive line opening over the die pad. A conductive material is deposited into the conductive line opening to form a conductive line. A second photoresist layer is deposited over the first layer, and the second layer is patterned to form a via opening over the conductive line. The conductive material is deposited into the via opening to form the conductive via, where the conductive material only deposits on portions of exposed conductive line. The second and first layers are removed. Portions of exposed seed layer are recessed, and then a top surface of the conductive via is exposed.
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