公开(公告)号：US06970394B2

公开(公告)日：2005-11-29

申请号：US10829689

申请日：2004-04-22

申请人： Shien-Yang Wu ,  Jhon-Jhy Liaw

发明人： Shien-Yang Wu ,  Jhon-Jhy Liaw

IPC分类号： G11C7/00 ,  G11C17/18

CPC分类号： G11C17/18

摘要： A programming method for fuse cells. A core circuit is applied with a first power voltage. The fuse cell includes an electrical fuse element connected to a common node, and a driver device connected between the electrical fuse element and a ground node. The ground node has a ground voltage. The fuse cell has a control gate for controlling current through the electrical fuse element. In program mode, a second power voltage is applied to the common node, a first control voltage is applied to the control gate of a selected fuse cell and a second control voltage is applied to the control gate of an unselected fuse cell. In read mode, the first power voltage is applied to the common node. The second power voltage exceeds the first power voltage. The second control voltage exceeds the ground voltage. The second control voltage is also lower than the first control voltage.

摘要翻译： 一种熔丝电池的编程方法。 核心电路采用第一电源电压。 熔丝单元包括连接到公共节点的电熔丝元件和连接在电熔丝元件和接地节点之间的驱动器件。 接地节点具有接地电压。 熔丝单元具有用于控制通过电熔丝元件的电流的控制栅极。 在编程模式下，向公共节点施加第二电源电压，将第一控制电压施加到所选择的熔丝单元的控制栅极，并且将第二控制电压施加到未选择的熔丝单元的控制栅极。 在读取模式下，第一个电源电压被施加到公共节点。 第二电源电压超过第一电源电压。 第二个控制电压超过接地电压。 第二控制电压也低于第一控制电压。

公开(公告)号：US20050111251A1

公开(公告)日：2005-05-26

申请号：US10723331

申请日：2003-11-26

申请人： Jhon-Jhy Liaw

发明人： Jhon-Jhy Liaw

IPC分类号： G11C11/34 ,  G11C11/412 ,  G11C16/04 ,  H01L21/8234 ,  H01L21/8244 ,  H01L27/092 ,  H01L27/10 ,  H01L27/11 ,  H01L29/78

CPC分类号： H01L27/11 ,  G11C11/412 ,  H01L27/1104 ,  Y10S257/903

摘要： A memory structure that reduces soft-errors for us in CMOS devices is provided. The memory cell layout utilizes transistors oriented such that the source-to-drain axis is parallel a shorted side of the memory cell. The dimensions of the memory cell are such that it has a longer side and a shorter side, wherein the longer side is preferably about twice as long as the shorter side. Such an arrangement uses a shorter well path to reduce the resistance between transistors and the well strap. The shorter well strap reduces the voltage during operation and soft errors.

摘要翻译： 提供了减少CMOS器件中的软错误的存储器结构。 存储单元布局利用以取向的晶体管使得源极到漏极轴平行于存储器单元的短路侧。 存储单元的尺寸使得其具有较长的侧面和较短的侧面，其中较长的侧面优选为短边的两倍长。 这种布置使用较短的井道以减小晶体管与井带之间的电阻。 较短的井带可以降低运行过程中的电压和软错误。

公开(公告)号：US06569723B2

公开(公告)日：2003-05-27

申请号：US10147222

申请日：2002-05-16

申请人： Jhon-Jhy Liaw

发明人： Jhon-Jhy Liaw

IPC分类号： H01L2100

CPC分类号： H01L27/1104 ,  H01L27/11 ,  Y10S257/903

摘要： This method forms an SRAM device with an array of cells having low resistance conductors for the reference potential (Vss) circuits connected to transistors in the SRAM device. First form an SRAM device with two pull-up transistors, two pull-down transistors and two pass gate transistors, including thin film gate electrode conductors and interconnection lines, each of the transistors having a drain region and a source region with source regions of the two pull-up transistors connected to a power supply voltage (Vcc). Then form a plurality of dielectric and metallization layers over the transistors, the conductors and the interconnection lines. Form a stack of layers over the transistors, the stack of layers comprising a plurality of metallization layers sandwiched between a plurality of dielectric layers. Form a conductive reference potential node electrically connected to the source region of each of the pull-down transistors. Form a first Vss strap/conductor in a first direction in a first one of the metallization layers. Form a second Vss strap/conductor in a second direction in a second one of the metallization layers. Form a VIA/contact between the conductive reference potential node and the first and second Vss strap conductors.

摘要翻译： 该方法形成具有低电阻导体的单元阵列的SRAM器件，用于连接到SRAM器件中的晶体管的参考电位（Vss）电路。 首先形成具有两个上拉晶体管的SRAM器件，两个下拉晶体管和两个通过栅极晶体管，其中包括薄膜栅极电极导体和互连线，每个晶体管具有漏极区域和源极区域，源区域为 两个上拉晶体管连接到电源电压（Vcc）。 然后在晶体管，导体和互连线上形成多个电介质和金属化层。 在晶体管上形成一叠层，层叠层包括夹在多个介电层之间的多个金属化层。 形成电连接到每个下拉晶体管的源极区域的导电参考电位节点。 在第一个金属化层中沿第一方向形成第一Vss带/导体。 在第二个金属化层中的第二个方向上形成第二个Vss带/导体。 在导电参考电位节点与第一和第二Vss带导体之间形成VIA /接触。

公开(公告)号：US06319758B1

公开(公告)日：2001-11-20

申请号：US09329783

申请日：1999-06-10

申请人： Jhon-Jhy Liaw

发明人： Jhon-Jhy Liaw

IPC分类号： H01L2182

CPC分类号： H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

摘要： A fuse link redundancy structure to implement redundant circuits within an integrated circuit has an insulating layer over a conductive layer of the fuse link is sufficiently thin and transparent to allow destruction of the conductive layer by an intense laser light. The redundancy structure has a fusible link formed of a layer of a conductive material deposited upon an insulating layer such as field oxide on the semiconductor substrate and connected between the redundant circuits and other circuits present on the integrated circuit. The layer of conductive material is either formed of a metal such as Aluminum or Tungsten, a heavily doped polycrystalline silicon, or an alloy of a metal such as Tungsten and a heavily doped polycrystalline silicon. A hard mask layer is placed upon the layer of conductive material during transistor processing to protect the layer of conductive material during formation of self-aligned sources and drains of transistors of the integrated circuit. The hard mask layer is removed from the layer of conductive layer for deposition of interlayer dielectric layers on the semiconductor substrate to improve a fuse destruction to implement the redundant circuits. An opening is formed in the interlayer dielectric layers to thin the interlayer dielectric layers to allow exposure of the layer of conductive material to facilitate destruction of the layer of conductive material.

公开(公告)号：US06174775B1

公开(公告)日：2001-01-16

申请号：US09344400

申请日：1999-06-25

申请人： Jhon-Jhy Liaw

发明人： Jhon-Jhy Liaw

IPC分类号： H01L21336

CPC分类号： H01L21/823835 ,  H01L21/823842

摘要： A process for fabricating a polycide, dual gate structure, for CMOS devices, featuring an undoped polysilicon layer, located between an overlying metal silicide layer, and an underlying dual doped polysilicon layer, has been developed. A first undoped polysilicon layer is converted to the dual doped polysilicon layer, via formation of an N type doped region, in a first portion of the first undoped polysilicon layer, overlying subsequent nMOS devices, in a P well region, followed by the formation of a P type doped region, in a second portion of the first undoped polysilicon layer, overlying subsequent pMOS devices, in an N well region. A second undoped polysilicon layer is deposited on the dual doped polysilicon layer, to provide a low diffusion coefficient buffer layer, to prevent auto-doping of the dual doped polysilicon layer, as a result of direct dopant diffusion into the overlying, high diffusion coefficient, metal silicide layer, followed by redistribution into the underlying dual doped polysilicon layer. The use of the undoped polysilicon, buffer layer, allows the use of high temperature procedures, such as procedures used with self-aligned contact structures, without the risk of the auto-doping phenomena.

摘要翻译： 已经开发了一种用于制造用于CMOS器件的多晶硅双栅极结构的工艺，其特征在于位于上覆金属硅化物层和下面的双掺杂多晶硅层之间的未掺杂多晶硅层。 第一未掺杂多晶硅层通过在第一未掺杂多晶硅层的第一部分中形成N型掺杂区域而被转换成双掺杂多晶硅层，覆盖在P阱区域中的后续nMOS器件，随后形成 在N阱区域中，在第一未掺杂多晶硅层的第二部分中覆盖随后的pMOS器件的P型掺杂区域。 第二未掺杂多晶硅层沉积在双掺杂多晶硅层上，以提供低扩散系数缓冲层，以防止双掺杂多晶硅层的自掺杂，这是由于直接掺杂剂扩散到上覆的高扩散系数， 金属硅化物层，然后再分配到下面的双掺杂多晶硅层中。 使用未掺杂的多晶硅缓冲层允许使用高温程序，例如与自对准接触结构一起使用的程序，而不会引起自动掺杂现象的风险。

公开(公告)号：US5920098A

公开(公告)日：1999-07-06

申请号：US148554

申请日：1998-09-04

申请人： Jhon-Jhy Liaw

发明人： Jhon-Jhy Liaw

IPC分类号： H01L21/768 ,  H01L29/76

CPC分类号： H01L21/76895

摘要： MOSFET devices, using a local interconnect structure, and silicon nitride capped, self-aligned contact openings, have been developed. The process features the creation of self-aligned contact openings, exposing specific source and drain regions. After deposition of a composite insulator layer, a second opening is formed in the composite insulator layer, again exposing various elements including the previously opened, specific source and drain regions. The local tungsten interconnect structure fills the second opening, contacts, as well as interconnects, the specific source and drain regions.

摘要翻译： 已经开发了使用局部互连结构的MOSFET器件和氮化硅封盖的自对准接触开口。 该过程的特征在于产生自对准的接触开口，暴露特定的源极和漏极区域。 在复合绝缘体层沉积之后，在复合绝缘体层中形成第二个开口，再次暴露出包括先前打开的特定源极和漏极区域的各种元件。 局部钨互连结构填充了特定的源极和漏极区域的第二个开口，触点以及互连。

公开(公告)号：US5904531A

公开(公告)日：1999-05-18

申请号：US933369

申请日：1997-09-19

申请人： Jhon-Jhy Liaw

发明人： Jhon-Jhy Liaw

IPC分类号： H01L21/74 ,  H01L21/336

CPC分类号： H01L27/11 ,  H01L21/743

摘要： A process for forming an increased surface area, buried contact region, for a MOSFET device, has been developed. The process features creating a mini-trench, in an insulator filled shallow trench, exposing a vertical surface of the semiconductor substrate, along the side of the mini-trench. An angled, phosphorous, ion implantation procedure, creates a buried contact region along a top surface, as well as along the vertical surface of the semiconductor substrate, exposed in the mini-trench.

摘要翻译： 已经开发了用于形成用于MOSFET器件的增加的表面积，掩埋接触区域的工艺。 该方法的特征是在绝缘体填充的浅沟槽中，沿着微沟槽侧面暴露出半导体衬底的垂直表面，形成微沟槽。 成角度的磷离子注入程序沿着顶表面以及暴露在微沟槽中的半导体衬底的垂直表面产生掩埋接触区域。

公开(公告)号：US5843815A

公开(公告)日：1998-12-01

申请号：US783984

申请日：1997-01-15

申请人： Jhon-Jhy Liaw

发明人： Jhon-Jhy Liaw

IPC分类号： H01L21/8244 ,  H01L27/11

CPC分类号： H01L27/11 ,  H01L27/1112

摘要： A process for fabricating a MOSFET device, for a triple polysilicon SRAM process, using a self-aligned, halo implant, (SAC halo implant), region, used to improve MOSFET performance and yield, has been developed. This process features implanting the SAC halo region, into a region of the semiconductor substrate, already exposed and prepared for a self-aligned contact, (SAC), structure, therefore requiring no additional photolithographic procedures.

摘要翻译： 已经开发了用于制造用于三重多晶硅SRAM工艺的MOSFET器件的工艺，其使用用于提高MOSFET性能和产量的自对准卤素注入（SAC卤素注入）区域。 该方法的特征在于将SAC晕区植入已经暴露并准备用于自对准接触（SAC）结构的半导体衬底的区域，因此不需要额外的光刻工艺。

公开(公告)号：US5705436A

公开(公告)日：1998-01-06

申请号：US703085

申请日：1996-08-26

申请人： Hsien Wei Chin ,  Jhon-Jhy Liaw

发明人： Hsien Wei Chin ,  Jhon-Jhy Liaw

IPC分类号： H01L21/02 ,  H01L21/8244

CPC分类号： H01L28/20 ,  H01L27/11

摘要： A physical implementation and method for achieving it are described for a load resistor and bus line subcircuit such as might be used in an SRAM cell. This was achieved by using two layers of polysilicon. The first polysilicon layer has low resistivity and serves to make effective contact to the drain regions of the FETs involved in the circuit. The second polysilicon layer has high resistivity and is used to form the load resistor as well as the collector bus line and resistor-drain connection. Formation of the latter two objects is achieved by providing a refractory metal underlay to the second polysilicon layer in the appropriate areas and then heating the structure so as to convert said refractory metal to its silicide. This process avoids the use of an ion implantation step during which some encroachment of the ions could occur, thereby retaining good control of the resistor dimensions.

摘要翻译： 描述了用于实现其的物理实现和方法，用于负载电阻器和总线线路电路，例如可用于SRAM单元。 这是通过使用两层多晶硅来实现的。 第一多晶硅层具有低电阻率并且用于有效接触与电路相关的FET的漏极区域。 第二多晶硅层具有高电阻率，用于形成负载电阻以及集电极母线和电阻 - 漏极连接。 后两个物体的形成是通过在合适的区域中向第二多晶硅层提供难熔金属底层，然后加热该结构以将所述难熔金属转化为其硅化物来实现的。 该过程避免使用离子注入步骤，在该步骤期间可能会发生一些离子侵入，从而保持对电阻器尺寸的良好控制。

公开(公告)号：US09036404B2

公开(公告)日：2015-05-19

申请号：US13436149

申请日：2012-03-30

申请人： Jhon-Jhy Liaw

发明人： Jhon-Jhy Liaw

IPC分类号： G11C11/00 ,  G06F17/50 ,  G11C11/412 ,  H01L27/02 ,  H01L27/11

CPC分类号： H01L27/1104 ,  G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  G11C11/412 ,  H01L27/0207 ,  H01L27/0924 ,  H01L27/11

摘要： An SRAM cell structure. In one embodiment, a bit cell first level contacts formed at a first and a second CVdd node, a first and a second CVss node, at a bit line node, at a bit line bar node, at a data node and at a data bar node; and second level contacts formed on each of the first level contacts at the first and second CVdd nodes, the first and second CVss nodes, the bit line node and the bit line bar node; wherein the first level contacts formed at the data node and the data bar node do not have a second level contact formed thereon. In another embodiment, a word line is formed and bit lines and a CVdd and a CVss line are formed overlying the SRAM cell and coupled to the corresponding ones of the nodes. Methods are disclosed for forming the cell structure.

摘要翻译： 一个SRAM单元结构。 在一个实施例中，在位线节点处，在位线条节点处，在数据节点处和在数据条上形成的位单元第一电平触点形成在第一和第二CVdd节点，第一和第二CVss节点 节点; 以及形成在第一和第二CVdd节点，第一和第二CVss节点，位线节点和位线条节点上的每个第一级触点上的第二级触点; 其中形成在所述数据节点和所述数据条节点处的所述第一级触点不具有形成在其上的第二级触点。 在另一个实施例中，形成字线，并且将位线和CVdd和CVss线形成在SRAM单元上并耦合到对应的节点。 公开了形成电池结构的方法。