公开(公告)号：US20080137244A1

公开(公告)日：2008-06-12

申请号：US11637108

申请日：2006-12-12

申请人： Kuo-Feng Yo ,  Jian-Hsing Lee ,  Jiaw-Ren Shih ,  Fu-Chin Yang

发明人： Kuo-Feng Yo ,  Jian-Hsing Lee ,  Jiaw-Ren Shih ,  Fu-Chin Yang

IPC分类号： H02H9/00

CPC分类号： H01L27/0262

摘要： An electrostatic discharge (ESD) protection circuit. The ESD protection circuit comprises a silicon controlled rectifier (SCR) device and a metal-oxide-semiconductor (MOS) triggering device. The SCR device has a cathode connected to a first fixed potential and an anode. The MOS triggering device has a gate and a source connected to the first fixed potential and a drain connected to the anode. In addition, the MOS triggering device is not physically disposed in the SCR device.

摘要翻译： 静电放电（ESD）保护电路。 ESD保护电路包括可控硅整流器（SCR）器件和金属氧化物半导体（MOS）触发器件。 SCR器件具有连接到第一固定电位和阳极的阴极。 MOS触发装置具有连接到第一固定电位的栅极和源极以及连接到阳极的漏极。 此外，MOS触发装置没有物理地设置在SCR装置中。

公开(公告)号：US07372083B2

公开(公告)日：2008-05-13

申请号：US11199662

申请日：2005-08-09

申请人： Jian-Hsing Lee ,  Yu-Chang Jong

发明人： Jian-Hsing Lee ,  Yu-Chang Jong

IPC分类号： H01L29/72

CPC分类号： H01L29/7393 ,  H01L27/0262 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/7436

摘要： A high voltage p-type metal oxide semiconductor (HVPMOS) device having electrostatic discharge (ESD) protection functions and a method of forming the same are provided. The HVPMOS includes a PMOS transistor, wherein the PMOS transistor comprises a first source/drain region doped with a p-type impurity in a high voltage p-well (HVPW) region, a second source/drain region doped with a p-type impurity in a high voltage n-well (HVNW) region wherein the HVPW region and HVNW region physically contact each other, a field region substantially underlying a gate dielectric, and a first heavily doped n-type (N+) region in the HVPW region and contacting the first source/drain region. The device further includes an N+ buried layer underlying the HVPW region and the HVNW region and a p-type substrate underlying the N+ buried layer. The device has robust performance for both forward and reverse mode ESD.

摘要翻译： 提供了具有静电放电（ESD）保护功能的高电压p型金属氧化物半导体（HVPMOS）器件及其形成方法。 HVPMOS包括PMOS晶体管，其中PMOS晶体管包括在高压p阱（HVPW）区域中掺杂有p型杂质的第一源极/漏极区域，掺杂有p型杂质的第二源极/漏极区域 在HVPW区域和HVNW区域彼此物理接触的场合，HVPW区域中基本上位于栅极电介质的场区域和第一重掺杂n型（N +）区域的高电压n阱（HVNW）区域中， 第一源极/漏极区域。 该器件还包括位于HVPW区域和HVNW区域下面的N +掩埋层和位于N +掩埋层下面的p型衬底。 该器件具有强大的正向和反向模式ESD性能。

公开(公告)号：US07179691B1

公开(公告)日：2007-02-20

申请号：US10207545

申请日：2002-07-29

申请人： Jian-Hsing Lee ,  Shui Hun Yi Chen

发明人： Jian-Hsing Lee ,  Shui Hun Yi Chen

IPC分类号： H01L21/332 ,  H01L21/331

CPC分类号： H01L27/0255

摘要： The invention describes a structure and a process for providing ESD semiconductor protection with reduced input capacitance. The structure consists of heavily doped P+ guard rings surrounding the I/O ESD protection device and the Vcc to Vss protection device. In addition, there is a heavily doped N+ guard ring surrounding the I/O protection device and its P+ guard ring. The guard rings enhance structure diode elements providing enhanced ESD energy discharge path capability enabling the elimination of a specific conventional Vss to I/O pad ESD protection device. This reduces the capacitance seen by the I/O circuit while still providing adequate ESD protection for the active circuit devices.

摘要翻译： 本发明描述了一种用于提供具有降低的输入电容的ESD半导体保护的结构和工艺。 该结构由围绕I / O ESD保护装置和Vcc至Vss保护装置的重掺杂P +保护环组成。 此外，还有一个围绕I / O保护器件及其P +保护环的重掺杂N +保护环。 保护环增强结构二极管元件，提供增强的ESD能量放电路径能力，从而能够消除特定的常规Vss至I / O焊盘ESD保护器件。 这降低了I / O电路所看到的电容，同时为有源电路器件提供足够的ESD保护。

公开(公告)号：US07154724B2

公开(公告)日：2006-12-26

申请号：US10812378

申请日：2004-03-29

申请人： Yi-Hsun Wu ,  Jian-Hsing Lee

发明人： Yi-Hsun Wu ,  Jian-Hsing Lee

IPC分类号： H02H9/04 ,  H01L23/62

CPC分类号： H01L27/0262

摘要： An input and output (I/O) circuit with an improved ESD protection is disclosed. The circuit has an output buffer having an NMOS transistor coupled to a PMOS transistor, an ESD protection circuit having a parasitic silicon controlled rectifier (SCR) integrated therein and coupled to the output buffer, and a diode string having a predetermined number of diodes coupled between a source node of the NMOS transistor and ground, wherein a voltage drop across the diode string increases the SCR gate holding voltage, thereby setting an ESD protection holding voltage for the ESD protection circuit.

摘要翻译： 公开了具有改进的ESD保护的输入和输出（I / O）电路。 电路具有输出缓冲器，其具有耦合到PMOS晶体管的NMOS晶体管，ESD保护电路具有集成在其中并耦合到输出缓冲器的寄生可控硅整流器（SCR），以及二极管串，其具有预定数量的二极管 NMOS晶体管的源节点并接地，其中二极管串上的电压降增加了SCR栅极保持电压，从而为ESD保护电路设置ESD保护保持电压。

公开(公告)号：US20060114629A1

公开(公告)日：2006-06-01

申请号：US11305983

申请日：2005-12-19

申请人： Yi-Hsun Wu ,  Jian-Hsing Lee ,  Shui-Hung Chen

发明人： Yi-Hsun Wu ,  Jian-Hsing Lee ,  Shui-Hung Chen

IPC分类号： H02H9/00

CPC分类号： H01L27/0266 ,  H01L2924/0002 ,  H01L2924/00

摘要： Input/output devices with robustness of ESD protection are provided. An input/output device comprises an input/output pad, a first NMOS transistor, a second NMOS transistor and an ESD detector. The first NMOS transistor comprises a first drain, a first source and a first gate, wherein the first source and the first gate are coupled to a first ground power rail, and the first drain to the input/output pad. The second NMOS transistor comprises a second drain, a second source and a second gate, wherein the second source is coupled to the first ground power rail, the second drain to the input/output pad, and the second gate to a first pre-driver. When an ESD event is detected, the ESD detector makes the first pre-driver couple the second gate to the first ground power rail, thereby the first and second transistors evenly discharge ESD current.

公开(公告)号：US20050254189A1

公开(公告)日：2005-11-17

申请号：US11091131

申请日：2005-03-28

申请人： Yi-Hsun Wu ,  Jian-Hsing Lee

发明人： Yi-Hsun Wu ,  Jian-Hsing Lee

IPC分类号： G01R27/02 ,  G11C17/16 ,  G11C17/18 ,  H01L27/02 ,  H01L29/00 ,  H01L29/74 ,  H02H9/00

CPC分类号： H01L27/0262 ,  G11C17/16 ,  G11C17/18 ,  H01L29/7436

摘要： An ESD protection circuit includes a silicon controlled rectifier coupled between a circuit pad and ground for bypassing an ESD current from the circuit pad during an ESD event. An MOS transistor, having a source shared with the silicon controlled rectifier, is coupled between the pad and ground for reducing a trigger voltage of the silicon controlled rectifier during the ESD event. The silicon controlled rectifier has a first diode serially connected to a second diode in an opposite direction, between the pad and the shared source of the MOS transistor, for functioning as a bipolar transistor. In a layout view, a first area for placement of the first and second diodes is interposed between at least two separate sets of second areas for placement of the MOS transistor.

摘要翻译： ESD保护电路包括耦合在电路焊盘和地之间的可控硅整流器，用于在ESD事件期间旁路来自电路板的ESD电流。 具有与可控硅整流器共享的源极的MOS晶体管耦合在焊盘和地之间，以在ESD事件期间降低可控硅整流器的触发电压。 可控硅整流器具有在与MOS晶体管的焊盘和共享源之间的相反方向上串联连接到第二二极管的第一二极管，用作双极晶体管。 在布局图中，用于放置第一和第二二极管的第一区域介于至少两个分开的第二区域组之间，用于放置MOS晶体管。

公开(公告)号：US20050237682A1

公开(公告)日：2005-10-27

申请号：US10831897

申请日：2004-04-26

申请人： Yi-Hsun Wu ,  Jian-Hsing Lee

发明人： Yi-Hsun Wu ,  Jian-Hsing Lee

IPC分类号： H01L27/02 ,  H02H9/00

CPC分类号： H01L27/0266

摘要： A circuit and a method for solving the general problem of protecting core devices in integrated circuits from electrostatic discharge damage is provided. This circuit and a method prevents ESD voltage breakdown of thin oxide field effect transistors which are directly connected to the core Vdd power supply. The embodiments of this invention use inverter buffers using a thick or thin oxide devices at the input to the core circuitry is to be protected. Other embodiments of this invention use pass transistor or transfer gates made with thick or thin oxide devices at the input to the core circuitry is to be protected.

摘要翻译： 提供了解决集成电路中的核心器件保护静电放电损坏的一般问题的电路和方法。 该电路和方法防止直接连接到核心Vdd电源的薄氧化物场效应晶体管的ESD电压击穿。 使用在核心电路的输入端使用厚或薄的氧化物装置的逆变器缓冲器的保护。 本发明的其它实施例使用传输晶体管或由厚或薄的氧化物器件制成的传输栅极在核心电路的输入端被保护。

公开(公告)号：US06879203B2

公开(公告)日：2005-04-12

申请号：US10821270

申请日：2004-04-08

申请人： Yi-Hsu Wu ,  Jian-Hsing Lee ,  Shui-Hung Chen

发明人： Yi-Hsu Wu ,  Jian-Hsing Lee ,  Shui-Hung Chen

IPC分类号： H01L23/62 ,  H01L27/02 ,  H01L29/74 ,  H01L29/768 ,  H03K5/08

CPC分类号： H01L27/0292 ,  H01L27/0251 ,  H01L2924/0002 ,  H01L2924/00

摘要： This invention provides two circuit embodiments for a whole chip electrostatic discharge, ECD, protection scheme. It also includes a method for whole chip ESD protection. This invention relates to distributing the circuit of this invention next to each input/output pad in order to provide parallel ESD current discharge paths. The advantage of this invention is the ability to create a parallel discharge path to ground in order to discharge the damaging ESD current quickly so as to avoid circuit damage. The two circuit embodiments show how the protection circuits of this invention at both the unzapped I/O pads and the zapped I/O pad are connected in a parallel circuit for discharging ESD currents quickly. These protection embodiments require a small amount of semiconductor area, since the smaller protection circuits are distributed and placed at the locations of each I/O pad.

摘要翻译： 本发明提供了用于整个芯片静电放电，ECD，保护方案的两个电路实施例。 它还包括一个全芯片ESD保护方法。 本发明涉及将本发明的电路分配给每个输入/输出焊盘，以便提供并联的ESD电流放电路径。 本发明的优点是能够快速地形成对地的平行放电路径，以便有效地放电损坏的ESD电流，以避免电路损坏。 两个电路实施例示出了本发明的保护电路如何在未分离的I / O焊盘和已加热的I / O焊盘两端均以并联电路连接，以快速放电ESD电流。 这些保护实施例需要少量的半导体区域，因为较小的保护电路分布并放置在每个I / O焊盘的位置。

公开(公告)号：US06803259B2

公开(公告)日：2004-10-12

申请号：US10404620

申请日：2003-03-31

申请人： Jian-Hsing Lee

发明人： Jian-Hsing Lee

IPC分类号： H01L21332

CPC分类号： H01L27/0262 ,  H01L29/74

摘要： A silicon controlled rectifier for SiGe process. The silicon controlled rectifier comprises a substrate, a buried layer of a first conductivity type in the substrate, a well of the first conductivity type in the substrate and above the buried layer, a doped region of a second conductivity type in the well, a first conducting layer of the second conductivity type on the substrate, and a second conducting layer of the first conductivity type on the first conducting layer.

公开(公告)号：US06784498B1

公开(公告)日：2004-08-31

申请号：US10403976

申请日：2003-03-31

申请人： Jian-Hsing Lee ,  Yi-Hsun Wu

发明人： Jian-Hsing Lee ,  Yi-Hsun Wu

IPC分类号： H01L2362

CPC分类号： H01L27/0262 ,  H01L29/0692 ,  H01L29/87

摘要： A low capacitance ESD protection device. The device comprises a substrate, a well of a first conductivity type in the substrate, a first and second transistor of the first conductivity type respectively on two sides of the well, a guard ring of a second conductivity type in the substrate, surrounding the well, and the first and second transistor, and a doped region of the second conductivity type in the well, wherein profiles of a drain and source region of each of the first and second transistor are un-symmetrical.

摘要翻译： 低电容ESD保护器件。 该器件包括衬底，衬底中的第一导电类型的阱，分别在阱的两侧上的第一导电类型的第一和第二晶体管，衬底中的第二导电类型的保护环，围绕阱 以及第一和第二晶体管，以及阱中的第二导电类型的掺杂区域，其中第一和第二晶体管中的每一个的漏极和源极区域的剖面是不对称的。