MTJ read head with sidewall spacers

    公开(公告)号:US20070252186A1

    公开(公告)日:2007-11-01

    申请号:US11825032

    申请日:2007-07-03

    Applicant: Lin Yang

    Inventor: Lin Yang

    CPC classification number: H01L43/12

    Abstract: Following CMP, a magnetic tunnel junction stack may protrude through the oxide that surrounds it, making it susceptible to possible shorting to its sidewalls. The present invention overcomes this problem by depositing silicon nitride spacers on these sidewalls prior to oxide deposition and CMP. So, even though the stack may protrude through the top surface of the oxide after CMP, the spacers serve to prevent possible later shorting to the stack.

    MRAM cell structure and method of fabrication

    公开(公告)号:US20060209591A1

    公开(公告)日:2006-09-21

    申请号:US11418910

    申请日:2006-05-05

    CPC classification number: G11C11/16 H01L27/222 H01L43/12

    Abstract: An MRAM structure is disclosed where the distance from a bit line or word line to an underlying free layer in an MTJ is small and well controlled. As a result, the bit line or word line switching current is reduced and tightly distributed for better device performance. A key feature in the method of forming the MRAM cell structure is a two step planarization of an insulation layer deposited on the MTJ array. A CMP step flattens the insulation layer at a distance about 60 to 200 Angstroms above the cap layer in the MTJ. Then an etch back step thins the insulation layer to a level about 50 to 190 Angstroms below the top of the cap layer. Less than 5 Angstroms of the cap layer is removed. The distance variation from the free layer to an overlying bit line or word line is within +/−5 Angstroms.

    A process for preparing lotus leaf extracts and method of use
    75.
    发明申请
    A process for preparing lotus leaf extracts and method of use 审中-公开
    制备莲叶提取物的方法及使用方法

    公开(公告)号:US20060182823A1

    公开(公告)日:2006-08-17

    申请号:US10906294

    申请日:2005-02-13

    CPC classification number: A61K36/48

    Abstract: This invention provides a process for extracting the flavonoid and alkaloid components from lotus leaf and provides a method for the reduction of body weight, total cholesterol (TC), low density lipoprotein (LDL) cholesterol, and triglycerides (TG). It also provides a method for increasing high density lipoprotein (HDL) cholesterol and the prevention of coronary heart disease (CHD). There are 10% to 80% flavones and 10% to 80% alkaloids in the lotus leaf extract powder of this invention. This process produces an improved standardized raw material that may be utilized as a single dietary supplement, food additive, or medicine and it may be added to other plant extracts, nutraceuticals, or pharmaceuticals.

    Abstract translation: 本发明提供从莲叶中提取类黄酮和生物碱成分的方法,提供降低体重,总胆固醇(TC),低密度脂蛋白(LDL)胆固醇和甘油三酸酯(TG)的方法。 它还提供了增加高密度脂蛋白(HDL)胆固醇和预防冠心病(CHD)的方法。 在本发明的莲花提取物粉末中有10%至80%的黄酮和10%至80%的生物碱。 该方法产生可用作单一膳食补充剂,食品添加剂或药物的改进的标准化原料,并且可以将其加入到其它植物提取物,营养品或药物中。

    Slow-release inhibitor for corrosion control of metals
    76.
    发明申请
    Slow-release inhibitor for corrosion control of metals 有权
    用于金属腐蚀控制的缓释抑制剂

    公开(公告)号:US20060091354A1

    公开(公告)日:2006-05-04

    申请号:US10981017

    申请日:2004-11-04

    Abstract: The present invention provides for a slow-release inhibitor that is applied to a metal surface, such as by way of a paint or primer coating, for corrosion control of the metal. An exemplary embodiment of the slow-release corrosion inhibitor includes a water-soluble particle, or pigment, and an organic polymeric film that encapsulates the particle. This water-soluble particle may be either organic or inorganic and, preferably, is non-carcinogenic and non-toxic. An additional water-soluble particle having an encapsulating, organic polymeric film further may be provided along with a water-soluble, organic compound to form the corrosion inhibitor. The polymeric film(s) are of a desired hydrophobicity and permeability to permit, upon interaction of the particle(s) with water, controlled diffusion of particle ions therethrough.

    Abstract translation: 本发明提供了一种缓释抑制剂,其被应用于金属表面,例如通过涂料或底漆涂层,用于金属的腐蚀控制。 缓释缓蚀剂抑制剂的一个示例性实施方案包括水溶性颗粒或颜料,以及包封颗粒的有机聚合物膜。 该水溶性颗粒可以是有机的或无机的,优选是非致癌的和无毒的。 还可以与水溶性有机化合物一起提供另外具有包封的有机聚合物膜的水溶性颗粒以形成腐蚀抑制剂。 聚合物膜具有所需的疏水性和渗透性,以便在颗粒与水相互作用时允许颗粒离子通过其控制扩散。

    MRAM cell structure and method of fabrication
    77.
    发明申请
    MRAM cell structure and method of fabrication 有权
    MRAM单元结构及其制造方法

    公开(公告)号:US20050260773A1

    公开(公告)日:2005-11-24

    申请号:US10849311

    申请日:2004-05-19

    CPC classification number: G11C11/16 H01L27/222 H01L43/12

    Abstract: An MRAM structure is disclosed where the distance from a bit line or word line to an underlying free layer in an MTJ is small and well controlled. As a result, the bit line or word line switching current is reduced and tightly distributed for better device performance. A key feature in the method of forming the MRAM cell structure is a two step planarization of an insulation layer deposited on the MTJ array. A CMP step flattens the insulation layer at a distance about 60 to 200 Angstroms above the cap layer in the MTJ. Then an etch back step thins the insulation layer to a level about 50 to 190 Angstroms below the top of the cap layer. Less than 5 Angstroms of the cap layer is removed. The distance variation from the free layer to an overlying bit line or word line is within +/−5 Angstroms.

    Abstract translation: 公开了一种MRAM结构,其中从位线或字线到MTJ中的下游自由层的距离小且受到良好控制。 因此,位线或字线切换电流减少并且分布紧密,从而更好的器件性能。 形成MRAM单元结构的方法中的一个关键特征是沉积在MTJ阵列上的绝缘层的两步平面化。 CMP步骤在MTJ的帽层上方约60至200埃的距离处使绝缘层平坦化。 然后,回蚀步骤将绝缘层沉降到帽层顶部下方约50至190埃的水平。 少于5埃的盖层被去除。 从自由层到上位线或字线的距离变化在+/- 5埃以内。

    [GRAPHICS DISPLAY ARCHITECTURE AND CONTROL CHIP SET THEREOF]
    78.
    发明申请
    [GRAPHICS DISPLAY ARCHITECTURE AND CONTROL CHIP SET THEREOF] 有权
    [图形显示结构及其控制芯片]

    公开(公告)号:US20050017980A1

    公开(公告)日:2005-01-27

    申请号:US10710095

    申请日:2004-06-18

    CPC classification number: G06F3/14

    Abstract: The graphics display architecture provided by the present invention comprises an AGP slot, a PCIE slot, and a control chip set. The control chip set comprises a plurality of multi-defined pins, which are electrically coupled to the first pins of the AGP slot and the second pins of the PCIE slot simultaneously. When the first graphics adapter is plugged in the AGP slot and the first graphics adapter complies with AGP interface specification, the multi-defined pins serve to send/receive the signal complied with AGP interface specification. When the first graphics adapter is plugged in the AGP slot and the first graphics adapter complies with the Gfx interface, the multi-defined pins serve to send/receive the signal complied with the Gfx interface. When the second graphics adapter is plugged in the PCIE slot, the multi-defined pins serve to send/receive the signal complied wit the PCIE interface specification.

    Abstract translation: 本发明提供的图形显示架构包括AGP槽,PCIE槽和控制芯片组。 控制芯片组包括多个多限定的引脚,它们同时电耦合到AGP插槽的第一引脚和PCIE插槽的第二引脚。 当第一个图形适配器插入AGP插槽并且第一个图形适配器符合AGP接口规范时,多重定义的引脚用于发送/接收符合AGP接口规范的信号。 当第一个图形适配器插入AGP插槽并且第一个图形适配器符合Gfx接口时,多重定义的引脚用于发送/接收符合Gfx接口的信号。 当第二个图形适配器插入PCIE插槽时,多重定义的引脚用于发送/接收符合PCIE接口规范的信号。

    One bit matched filter with low complexity and high speed
    79.
    发明授权
    One bit matched filter with low complexity and high speed 有权
    一个位匹配滤波器,复杂度低,速度快

    公开(公告)号:US6157684A

    公开(公告)日:2000-12-05

    申请号:US172973

    申请日:1998-10-14

    CPC classification number: H04B1/7093 G06F17/15

    Abstract: Described is an one bit matched filter for generating a sequences of correlations between a signal bit stream and a sample stream of n sample bits. The n sample bits are arranged in a rang of n bit positions n, n-1, . . . , 2, 1. Among the n sample bits, m boundary positions are defined based on the bit pattern of the sample stream, where m

    Abstract translation: 描述了一个一比特匹配滤波器,用于产生信号比特流和n个采样比特的采样流之间的相关序列。 n个采样位以n位n,n-1的排列排列。 。 。 ,2,1。在n个采样位中,m个边界位置基于样本流的位模式来定义,其中m

    Cellular neural network
    80.
    发明授权
    Cellular neural network 失效
    细胞神经网络

    公开(公告)号:US5140670A

    公开(公告)日:1992-08-18

    申请号:US417728

    申请日:1989-10-05

    CPC classification number: G06N3/0635 G06N3/04

    Abstract: A novel class of information-processing systems called a cellular neural network is discussed. Like a neural network, it is a large-scale nonlinear analog circuit which processes signals in real time. Like cellular automata, it is made of a massive aggregate of regularly spaced circuit clones, called cells, which communicate with each other directly only through its nearest neighbors. Each cell is made of a linear capacitor, a nonlinear voltage-controlled current source, and a few resistive linear circuit elements. Cellular neural networks share the best features of both worlds; its continuous time feature allows real-time signal processing found within the digital domain and its local interconnection feature makes it tailor made for VLSI implementation. Cellular neural networks are uniquely suited for high-speed parallel signal processing.

    Abstract translation: 讨论了一类称为细胞神经网络的信息处理系统。 像神经网络一样,它是一个实时处理信号的大规模非线性模拟电路。 像细胞自动机一样,它由大量的规则间隔的电路克隆组成,称为单元,其仅通过其最近的邻居直接相互通信。 每个单元由线性电容器,非线性压控电流源和少数电阻线性电路元件组成。 细胞神经网络共享两个世界的最佳特征; 其连续的时间特征允许在数字域内发现实时信号处理,并且其本地互连功能使其适合VLSI实现。 蜂窝神经网络独特地适用于高速并行信号处理。

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