公开(公告)号：US20250156107A1

公开(公告)日：2025-05-15

申请号：US19025860

申请日：2025-01-16

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts

IPC: G06F3/06

Abstract: Methods, systems, and devices for performance monitoring for a memory system are described. A memory system may use a set of counters to determine state information for the memory system. The memory system may also use a set of timers to determine latency information for the memory system. In response to a request for performance information, the memory system may transmit state information, latency information, or both to a host system.

公开(公告)号：US12242743B2

公开(公告)日：2025-03-04

申请号：US17970132

申请日：2022-10-20

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts ,  Haojie Ye

IPC: G06F3/06

Abstract: Disclosed in some examples are systems, devices, machine-readable mediums, and methods for customizing an in-memory versioning mode for each memory location according to a predicted access behavior to optimize memory device performance. Usage data in a previous time period may be utilized along with policy rules to determine whether to configure a particular memory address as a zero copy or direct copy mode. For example, memory addresses that are read frequently may be configured as direct copy mode to reduce the read latency penalty. This improves the functioning of the memory system by reducing read latency for memory addresses that are frequently read but written to less frequently, and reduces write latency for memory locations that are frequently written to, but not read as frequently.

公开(公告)号：US12204789B2

公开(公告)日：2025-01-21

申请号：US17897886

申请日：2022-08-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： David Andrew Roberts

IPC: G06F3/06

Abstract: A system includes a memory device and a processing device coupled to the memory device, and the processing device is to perform operations including determining, by monitoring accesses to the memory device, a plurality of values of one or more memory usage statistics reflecting memory usage by a plurality of requestors connected to the memory sub-system; generating memory usage data by processing the plurality of values of the one or more memory usage statistics; and transmitting, to a requestor of the plurality of requestors, the memory usage data.

公开(公告)号：US20250004668A1

公开(公告)日：2025-01-02

申请号：US18639716

申请日：2024-04-18

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts

IPC: G06F3/06 ,  G06F12/0862

Abstract: Methods, systems, and devices for inter-tier metadata storage are described. A controller associated with a memory system may manage metadata storage across tiers of memory within the memory system or across memory systems. The controller may transfer metadata between tiers of memory based on whether an access count associated with the metadata satisfies a threshold. For example, the controller may transfer metadata from a first tier of memory to a second tier of memory if the access count satisfies a threshold count. The controller may transfer the metadata from the second tier of memory to the first tier of memory if the access count fails to satisfy the threshold count.

公开(公告)号：US20240330115A1

公开(公告)日：2024-10-03

申请号：US18600256

申请日：2024-03-08

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts

IPC: G06F11/14 ,  G06F11/07

CPC classification number: G06F11/1451 ,  G06F11/076 ,  G06F11/0772 ,  G06F11/1458

Abstract: Methods, systems, and devices for management and control for ephemeral data are described. A host system may configure a memory device of a memory system to store ephemeral data. The host system may configure the memory device for a performance mode, which may include suspending memory management operations of a portion of the memory device based on allocating the portion for storing the ephemeral data. After storing the ephemeral data to the portion, the memory system may perform an error control procedure to identify one or more errors in the ephemeral data. The memory system may transmit an indication of the one or more errors to the host system, where the host system may determine to ignore the errors, or transfer back-up ephemeral data to the portion of the memory device from another portion of the memory device or from another memory device of the memory system.

公开(公告)号：US20240231684A9

公开(公告)日：2024-07-11

申请号：US17972822

申请日：2022-10-25

Applicant: Micron Technology, Inc.

Inventor： Haojie Ye ,  David Andrew Roberts

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0607 ,  G06F3/0679

Abstract: Devices and techniques for continuous in-memory versioning are described herein. A memory subsystem includes a memory device configured to store a first data unit, a second data unit, and a third data unit, wherein the first, second, and third data units have a set of physical memory locations on the memory device, and metadata associated with the first, second, and third data units, the metadata including state information and a dirty commit timestamp; and a processing device, operatively coupled to the memory device, the processing device configured to: receive, from a host system, a first memory command associated with a logical memory address, the logical memory address mapped to the set of physical memory locations of the memory device; and in response to receiving the first memory command, perform a data operation on the first, second, or third data unit based on the state information and the dirty commit timestamp.

公开(公告)号：US20240070072A1

公开(公告)日：2024-02-29

申请号：US17896883

申请日：2022-08-26

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts

IPC: G06F12/0815

CPC classification number: G06F12/0815 ,  G06F2212/1032 ,  G06F2212/305

Abstract: An access counter associated with a segment of a memory device is maintained. An access notification for a first line of the segment is received. An access type associated with the access notification is identified. A first value of the access counter is changed by a second value based on the access type. Based on the first value of the access counter, a memory management scheme is implemented.

公开(公告)号：US11886728B2

公开(公告)日：2024-01-30

申请号：US17836529

申请日：2022-06-09

Applicant: Micron Technology, Inc.

Inventor： Tony M. Brewer ,  David Boles ,  David Andrew Roberts

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0619 ,  G06F3/0631 ,  G06F3/0659 ,  G06F3/0673

Abstract: Disclosed in some examples are methods, systems, memory devices, and machine-readable mediums that allows an application thread to indicate an undo logging operation when calculations are beginning that may need to be rolled back if a crash or other failure occurs. During the undo logging operation, memory writes an identified memory are done to a copy and the original value is preserved. If the undo logging operation is committed, then the copy becomes the correct value and may then be subsequently used in place of the original, or the value stored in the copy is copied to the original. If the undo logging operation is abandoned, the copy is not preserved and the value goes back to the original.

公开(公告)号：US20230350598A1

公开(公告)日：2023-11-02

申请号：US17661244

申请日：2022-04-28

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts

IPC: G06F3/06

CPC classification number: G06F3/0653 ,  G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

Abstract: Methods, systems, and devices for performance monitoring for a memory system are described. A memory system may use a set of counters to determine state information for the memory system. The memory system may also use a set of timers to determine latency information for the memory system. In response to a request for performance information, the memory system may transmit state information, latency information, or both to a host system.

公开(公告)号：US11797198B2

公开(公告)日：2023-10-24

申请号：US17238791

申请日：2021-04-23

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0631 ,  G06F3/0605 ,  G06F3/0647 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0238 ,  G06F12/0292

Abstract: Various embodiments provide for one or more processor instructions and memory instructions that enable a memory sub-system to copy, move, or swap data across (e.g., between) different memory tiers of the memory sub-system, where each of the memory tiers is associated with different memory locations (e.g., different physical memory locations) on one or more memory devices of the memory sub-system.