中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

122 records (took 0.028 seconds)

    VERIFICATION OF A VOLATILE MEMORY USING A UNIQUE IDENTIFIER
    71.
    发明公开
    VERIFICATION OF A VOLATILE MEMORY USING A UNIQUE IDENTIFIER 审中-公开

    公开(公告)号：US20230205430A1

    公开(公告)日：2023-06-29

    申请号：US17694355

    申请日：2022-03-14

    Applicant: Micron Technology, Inc.

    Inventor： Aaron Boehm ,  Jeremy Chritz ,  David Hulton ,  Tamara Schmitz ,  Max Vohra

    IPC: G06F3/06

    CPC classification number: G06F3/0619 ,  G06F3/0659 ,  G06F3/0679

    Abstract: Methods, systems, and devices for verification of a volatile memory, such as a dynamic random-access memory (DRAM), using a unique identifier (ID) are described. A memory device may store a unique ID for a DRAM component of the memory device in non-volatile memory (e.g., in the DRAM, external to the DRAM). A host device coupled with the memory device may store, to non-volatile memory at the host device, information for verifying the identity of the DRAM component, for example, based on the unique ID. The memory device and host device may perform a procedure for verification of the identity of the DRAM component using the unique ID of the DRAM and the verification information stored at the host device. If the host device detects that the DRAM has been replaced or modified based on the verification procedure, the host device may disable one or more features of the memory device.

    ATTESTATION LOGIC ON MEMORY FOR MEMORY DIE VERIFICATION
    73.
    发明申请
    ATTESTATION LOGIC ON MEMORY FOR MEMORY DIE VERIFICATION 有权

    公开(公告)号：US20230119361A1

    公开(公告)日：2023-04-20

    申请号：US18068419

    申请日：2022-12-19

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Jeremy Chritz ,  David Hulton ,  Tamara Schmitz

    IPC: H04L9/08 ,  H04L9/32 ,  H03K19/17768

    Abstract: Examples described herein provide for attestation of memory dies using a respective memory identifier of the memory die itself. A memory device may include a memory die with a memory array, attestation logic, and programmable circuitry that stores a memory identifier associated with the memory array. The attestation logic may generate an encryption key pair based on the memory identifier stored in the programmable circuitry. Advantageously, by attesting memory die using a memory identifier stored in programmable circuitry, examples of systems and methods described herein may provide increased security for data processed by memory die. For example, a non-attested or compromised memory die may be remediated. The attestation of memory dies may include attestation of memory dies on wireless devices, drones, vehicles, and/or Internet-of-Things devices.

    MEMORY DEVICES AND METHODS WHICH MAY FACILITATE TENSOR MEMORY ACCESS
    75.
    发明申请
    MEMORY DEVICES AND METHODS WHICH MAY FACILITATE TENSOR MEMORY ACCESS 有权

    公开(公告)号：US20220398190A1

    公开(公告)日：2022-12-15

    申请号：US17888748

    申请日：2022-08-16

    Applicant: Micron Technology, Inc.

    Inventor： Fa-Long Luo ,  Jaime Cummins ,  Tamara Schmitz ,  Jeremy Chritz

    IPC: G06F12/02 ,  G06F12/0893 ,  G06F12/0864

    Abstract: Methods, apparatuses, and systems for tensor memory access are described. Multiple data located in different physical addresses of memory may be concurrently read or written by, for example, employing various processing patterns of tensor or matrix related computations. A memory controller, which may comprise a data address generator, may be configured to generate a sequence of memory addresses for a memory access operation based on a starting address and a dimension of a tensor or matrix. At least one dimension of a tensor or matrix may correspond to a row, a column, a diagonal, a determinant, or an Nth dimension of the tensor or matrix. The memory controller may also comprise a buffer configured to read and write the data generated from or according to a sequence of memory of addresses.

    Wireless devices and systems including examples of compensating power amplifier noise
    76.
    发明授权
    Wireless devices and systems including examples of compensating power amplifier noise 有权

    公开(公告)号：US11528043B2

    公开(公告)日：2022-12-13

    申请号：US17162992

    申请日：2021-01-29

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Fa-Long Luo ,  Jeremy Chritz ,  Jaime Cummins ,  Tamara Schmitz

    IPC: H04B1/04 ,  H04L1/00 ,  H03M13/15 ,  H04L5/14 ,  H04L5/00 ,  H04B1/12 ,  H04B1/525

    Abstract: Examples described herein include methods, devices, and systems which may compensate input data for non-linear power amplifier noise to generate compensated input data. In compensating the noise, during an uplink transmission time interval (TTI), a switch path is activated to provide amplified input data to a receiver stage including a coefficient calculator. The coefficient calculator may calculate an error representative of the noise based partly on the input signal to be transmitted and a feedback signal to generate coefficient data associated with the power amplifier noise. The feedback signal is provided, after processing through the receiver, to a coefficient calculator. During an uplink TTI, the amplified input data may also be transmitted as the RF wireless transmission via an RF antenna. During a downlink TTI, the switch path may be deactivated and the receiver stage may receive an additional RF wireless transmission to be processed in the receiver stage.

    Memory systems including examples of calculating hamming distances for neural network and data center applications
    78.
    发明授权
    Memory systems including examples of calculating hamming distances for neural network and data center applications 有权

    公开(公告)号：US11449276B2

    公开(公告)日：2022-09-20

    申请号：US17016023

    申请日：2020-09-09

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： David Hulton ,  Jeremy Chritz ,  Tamara Schmitz

    IPC: G06K9/62 ,  G06F3/06 ,  G06F13/16 ,  H04L9/06 ,  G06N3/08

    Abstract: Examples of systems and method described herein provide for the processing of image codes (e.g., a binary embedding) at a memory system including a Hamming processing unit. Such images codes may generated by various endpoint computing devices, such as Internet of Things (IoT) computing devices, Such devices can generate a Hamming processing request, having an image code of the image, to compare that representation of the image to other images (e.g., in an image dataset) to identify a match or a set of neural network results. Advantageously, examples described herein may be used in neural networks to facilitate the processing of datasets, so as to increase the rate and amount of processing of such datasets. For example, comparisons of image codes can be performed “closer” to the memory devices, e.g., at a processing unit having memory devices.

    Neural networks and systems for decoding encoded data
    80.
    发明授权
    Neural networks and systems for decoding encoded data 有权

    公开(公告)号：US11416735B2

    公开(公告)日：2022-08-16

    申请号：US16839447

    申请日：2020-04-03

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Fa-Long Luo ,  Jaime Cummins ,  Tamara Schmitz

    IPC: G06N3/04 ,  H03M13/11 ,  H03M13/15 ,  G06K9/62 ,  G06F17/18 ,  G06N3/08

    Abstract: Examples described herein utilize multi-layer neural networks to decode encoded data (e.g., data encoded using one or more encoding techniques). The multi-layer neural networks include an encoder configured to encode input data using encoded bits in accordance with an encoding technique and to provide encoded input data, and a memory configured to receive the encoded input data from the encoder and configured to store the encoded input data. The multi-layer neural networks further include combiners configured to receive the encoded input data from the memory and further configured to combine the encoded input data among a set of predetermined weights. The combiners are further configured to provide encoded data with reduced noise, the noise introduced by the memory.

Patent Agency Ranking