公开(公告)号：US11984186B2

公开(公告)日：2024-05-14

申请号：US17454443

申请日：2021-11-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： David Hulton ,  Tamara Schmitz ,  Jonathan D. Harms ,  Jeremy Chritz ,  Kevin Majerus

IPC: G11C29/00 ,  G06F3/06 ,  G06F12/02 ,  G06F12/126 ,  G06F11/10 ,  G06F12/0813 ,  G11C11/408 ,  G11C11/418 ,  G11C29/04 ,  G11C29/44 ,  H04L61/2575

CPC classification number: G11C29/76 ,  G06F3/0659 ,  G06F12/0246 ,  G06F12/126 ,  G06F11/1048 ,  G06F12/0813 ,  G11C11/408 ,  G11C11/418 ,  G11C29/04 ,  G11C29/44 ,  G11C29/4401 ,  G11C29/787 ,  H04L61/2575

Abstract: Methods, apparatuses, and systems for repairing defective memory cells in regions of a memory array associated with high or low priority levels are disclosed. A repair address generator may be configured to generate a memory address map for repair (e.g., blowing fuses at a fuse circuit), depending on whether certain applications may operate at a high priority level indicative of a low bit error rate or a low priority level indicative of a higher bit error rate. For example, a specified error rate associated with a low priority level may correspond to a threshold error rate for certain applications, such as a neural network application that stores trained weights. Such neural network applications may access trained weights being partially stored in defective memory cells, with the least significant bits of such trained weights being stored in defective memory cells that are not repaired according to the memory address map.

公开(公告)号：US11899829B2

公开(公告)日：2024-02-13

申请号：US17108934

申请日：2020-12-01

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jeremy Chritz ,  David Hulton

IPC: G06F21/79 ,  G06F21/44 ,  G06F21/31 ,  G06F21/60 ,  G06F13/16 ,  H04L9/06 ,  G06F12/14

CPC classification number: G06F21/79 ,  G06F12/1433 ,  G06F13/1668 ,  G06F21/31 ,  G06F21/602 ,  G06F21/604 ,  H04L9/0643

Abstract: Examples of systems and method described herein or generating, in a memory controller and/or memory device, access codes for memory regions of the memory device using authentication logic, and for accessing the memory device using the access codes. For example, a memory controller and/or a coupled memory device may generate access codes that a host computing device may include in a memory access request to access one or more memory regions of the memory device. Data read or written at the memory device may in some examples only be accessed in accordance with the access codes for memory regions of the memory device. Accordingly, the systems and methods described herein may provide security for specific memory regions of a memory device because the access code are updated periodically (e.g., based on obtained reset indication) or in accordance with an updated count value from a counter.

公开(公告)号：US20230063890A1

公开(公告)日：2023-03-02

申请号：US17459543

申请日：2021-08-27

Applicant: Micron Technology, Inc.

Inventor： Aaron Boehm ,  Jeremy Chritz ,  Tamara Schmitz ,  David Hulton ,  Max Vohra

IPC: G06F21/55 ,  G06F3/06

Abstract: Methods, systems, and devices for measuring change in a channel characteristic to detect a memory device attack are described. A system, such as a vehicle system, may include a host device coupled with a memory device. The host device may transmit a first signal to the memory device and may receive, from the memory device, a second signal as feedback based on the first signal. The host device may determine a channel characteristic, such as a channel impedance measurement, based on the second signal received from the memory device. If the determined channel characteristic fails to satisfy a threshold (e.g., if the measured channel impedance fails to satisfy a reference value within a tolerance range), the host device may detect a potential attack on the memory device and may take corrective action, such as disabling one or more features of the memory device.

公开(公告)号：US10761847B2

公开(公告)日：2020-09-01

申请号：US16104341

申请日：2018-08-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： David Hulton

IPC: G06F9/30

Abstract: An apparatus in a configurable logic unit may include a configurable logic unit (CLU) configured to receive first and second operands and to perform an operand operation and generate an operation value. The apparatus may also include: a random value generator for generating a random value; an adder coupled to the CLU and the random value generator and configured to generate a sum of the operation value and the random value; and a shift register coupled to the adder and configured to shift the sum by a number of bits to generate shifted data at an output. The random value generator may be a linear feedback shift register. The output may be coupled to an additional CLU so that the shifted data may be used for subsequent operand operations. The apparatus may be implemented in a digital signal processor slice in a configurable logic block.

公开(公告)号：US20200034309A1

公开(公告)日：2020-01-30

申请号：US16049269

申请日：2018-07-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jeremy Chritz ,  David Hulton

IPC: G06F12/10 ,  G06F3/06

Abstract: Apparatuses and methods for managing a coherent memory are described. These may include one or more algorithmic logic units (ALUs) and an input/output (IO) interface. The I/O interface may receive one or more commands and retrieve data from or write data to a memory device. Each command may contain a memory address portion associated with a memory device. The apparatus may also include a memory mapping unit and a device controller. The memory mapping unit may map the memory address to a memory portion of the memory device, and the device controller may communicate with the memory device to retrieve data from or write data to the memory device. The apparatus may be implemented as a processing element in a configurable logic block network, which may additionally include a control logic unit that receives programming instructions from an application and generate the one or more commands based on the instructions.

公开(公告)号：US10516606B2

公开(公告)日：2019-12-24

申请号：US15647676

申请日：2017-07-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jeremy Chritz ,  David Hulton ,  John Schroeter ,  John Watson

IPC: H04L12/721 ,  H04L12/715 ,  H04L12/733 ,  H04L12/707

Abstract: A device comprising a plurality of antennas operable to transmit and receive communication packets via a plurality of communication protocols and an integrated circuit chip coupled to the plurality of antennas. The integrated circuit chip comprises a first and a second plurality of processing elements. The first plurality of processing elements operable to receive communication packets via a first one of a plurality of communication protocols and process an optimal route. The second plurality of processing elements communicatively coupled to the first plurality of processing elements and operable to determine the optimal route to transmit the communication packets from a source device to a destination device based, at least in part, on transmission characteristics associated with at least one of the source or destination devices.

公开(公告)号：US11899942B2

公开(公告)日：2024-02-13

申请号：US18146120

申请日：2022-12-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jeremy Chritz ,  David Hulton

IPC: G06F3/06 ,  G06F12/0877 ,  H04L9/06

CPC classification number: G06F3/0622 ,  G06F3/0655 ,  G06F3/0679 ,  G06F12/0877 ,  H04L9/0631 ,  G06F2212/60

Abstract: Examples of systems and method described herein provide for accessing memory devices and, concurrently, generating access codes using an authenticated stream cipher at a memory controller. For example, a memory controller may use a memory access request to, concurrently, perform translation logic and/or error correction on data associated with the memory access request; while also utilizing the memory address as an initialization vector for an authenticated stream cipher to generate an access code. The error correction may be performed subsequent to address translation for a write operation (or prior to address translation for a read operation) to improve processing speed of memory access requests at a memory controller; while the memory controller also generates the encrypted access code.

公开(公告)号：US20230367575A1

公开(公告)日：2023-11-16

申请号：US17744350

申请日：2022-05-13

Applicant: Micron Technology, Inc.

Inventor： Niccolo Izzo ,  Alessandro Orlando ,  Danilo Caraccio ,  David Hulton

IPC: G06F8/65 ,  H04L9/08

CPC classification number: G06F8/65 ,  H04L9/088

Abstract: Methods, systems, and devices for techniques for managing offline identity upgrades are described. A memory system may receive a command to update a device identifier for a device identifier composition engine (DICE) associated with the memory system. The memory system may generate an updated device identifier, at a first software layer of a set of software layers of the DICE, based on receiving the command. The memory system may decrypt a device specific key (DSK) stored at a read-only memory device of the memory system based on the received command, and sign the updated device identifier using the DSK based on decrypting the DSK. The memory system may execute one or more operations associated with the first software layer of the set of software layers of the DICE based on the signed updated device identifier.

公开(公告)号：US20230205873A1

公开(公告)日：2023-06-29

申请号：US17653264

申请日：2022-03-02

Applicant: Micron Technology, Inc.

Inventor： Aaron P. Boehm ,  David Hulton ,  Jeremy Chritz ,  Tamara Schmitz ,  Max S. Vohra

IPC: G06F21/55 ,  G06N20/00 ,  G06F3/06

CPC classification number: G06F21/554 ,  G06N20/00 ,  G06F3/0655 ,  G06F3/0604 ,  G06F3/0673 ,  G06F2221/034 ,  G06F9/4411

Abstract: Methods, systems, and devices for training procedure change determination to detect an attack are described. A host device may perform one or more training procedures to train aspects of a memory device (e.g., a dynamic random-access memory (DRAM) component). A training procedure may depend on a current (e.g., present, within a threshold duration) metric associated with the memory device, such as a current channel metric for a channel between the memory device and the host device. The host device, memory device, or another device, may store a set of reference values associated with a training procedure and may compare a result of a training procedure to a reference value of the set to determine whether the training procedure has changed. If the training procedure or a related value has changed, the memory device may disable one or more features of the memory device to protect against a potential attack.

公开(公告)号：US11269661B2

公开(公告)日：2022-03-08

申请号：US16292091

申请日：2019-03-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jeremy Chritz ,  Tamara Schmitz ,  Fa-Long Luo ,  David Hulton

IPC: G06F15/82 ,  G06F9/38 ,  G06F9/448 ,  G06F12/0842 ,  G06F9/50

Abstract: Methods, apparatuses, and systems for implementing data flows in a processor are described herein. A data flow manager may be configured to generate a configuration packet for a compute operation based on status information regarding multiple processing elements of the processor. Accordingly, multiple processing elements of a processor may concurrently process data flows based on the configuration packet. For example, the multiple processing elements may implement a mapping of processing elements to memory, while also implementing identified paths, through the processor, for the data flows. After executing the compute operation at certain processing elements of the processor, the processing results may be provided. In speech signal processing operations, the processing results may be compared to phonemes to identify such components of human speech in the processing results. Once dynamically identified, the processing elements may continue comparing additional components of human speech to facilitate processing of an audio recording, for example.