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    Method of checking a capacitive actuator
    71.
    发明授权
    Method of checking a capacitive actuator 有权
    检查电容式致动器的方法

    公开(公告)号：US06349705B1

    公开(公告)日：2002-02-26

    申请号：US09521500

    申请日：2000-03-09

    Applicant: Richard Pirkl ,  Achim Przymusinski ,  Walter Schrod ,  Mark Elliott

    Inventor： Richard Pirkl ,  Achim Przymusinski ,  Walter Schrod ,  Mark Elliott

    IPC: F02M5100

    CPC classification number: F02D41/221 ,  F02D41/2096 ,  H01L41/042 ,  H02N2/06

    Abstract: A capacitive actuator is driven with a control signal st. The duration ti of actual actuator actuation is compared with the duration tst of the control signal st. Proper operation is determined, and the actuator is assumed to be operating correctly, if the measured duration ti is within a range determined by the duration tst of the control signal.

    Abstract translation: 电容式致动器由控制信号st驱动。 将实际致动器致动的持续时间ti与控制信号st的持续时间tst进行比较。 如果测量的持续时间ti在由控制信号的持续时间tst确定的范围内，则确定正确的操作，并且假设致动器正常工作。

    Transceiver and method for operating the transceiver
    72.
    发明授权
    Transceiver and method for operating the transceiver 有权
    收发器和操作收发器的方法

    公开(公告)号：US07961015B2

    公开(公告)日：2011-06-14

    申请号：US10888770

    申请日：2004-07-09

    Applicant: Mark Elliott ,  Christoph Kleiner ,  Wolfgang Reiml ,  Dieter Saβ ,  Peter Turban ,  Herbert Zimmer

    Inventor： Mark Elliott ,  Christoph Kleiner ,  Wolfgang Reiml ,  Dieter Saβ ,  Peter Turban ,  Herbert Zimmer

    IPC: H03B1/00 ,  H03B3/00

    CPC classification number: H04B5/02 ,  Y02D70/166 ,  Y02D70/42

    Abstract: The transceiver features a fast de-excitation circuit, by means of which the transceiver can be very quickly de-energized or de-excited after sending of signals. The fast de-excitation circuit can be realized in the simplest case as a controllable switch with series-connected resistor. The transceiver is thus ready to receive signals again very fast, i.e. in the range of a few oscillation periods. With bidirectional data communication between transceiver and transponder the danger of malfunctions is avoided or at least reduced to a minimum level.

    Abstract translation: 收发器具有快速去激励电路，通过该电路，发送信号后收发器可以非常快速地断电或去激励。 快速去激励电路可以在最简单的情况下实现为具有串联电阻器的可控开关。 因此，收发器准备好再次非常快地接收信号，即在几个振荡周期的范围内。 通过收发器和应答器之间的双向数据通信，避免了故障的危险，或至少降低到最低水平。

    Aralkyl and aralkylidene heterocyclic lactam and imides
    78.
    发明申请
    Aralkyl and aralkylidene heterocyclic lactam and imides 审中-公开
    芳烷基和亚烷基杂环内酰胺和酰亚胺

    公开(公告)号：US20050227980A1

    公开(公告)日：2005-10-13

    申请号：US11011912

    申请日：2004-12-14

    Applicant: Harry Howard ,  Mark Elliott

    Inventor： Harry Howard ,  Mark Elliott

    IPC: A61K31/5377 ,  C07D413/02 ,  C07D413/10

    CPC classification number: C07D413/10

    Abstract: The present invention relates to compounds of the formula I wherein R1, R2, R3, X, Y and the dashed line are as defined in the specification, to intermediates for their preparation, to pharmaceutical compositions containing them and to their medicinal use as psychotherapeutic agents.

    Abstract translation: 本发明涉及式I化合物，其中R 1，R 2，R 3，X，Y和虚线为 在说明书中定义为制备中间体，含有它们的药物组合物和作为精神治疗药物的药物组合物。

    Method and device for driving a power output stage
    79.
    发明授权
    Method and device for driving a power output stage 失效
    用于驱动功率输出级的方法和装置

    公开(公告)号：US06556407B2

    公开(公告)日：2003-04-29

    申请号：US09873648

    申请日：2001-06-04

    Applicant: Cyrille Brando ,  Mark Elliott ,  Johann Falter

    Inventor： Cyrille Brando ,  Mark Elliott ,  Johann Falter

    IPC: H02H300

    CPC classification number: H03K17/04206 ,  H03K17/166

    Abstract: In order to drive it with compatible electromagnetic interference, a circuit breaker is charged with a high charging current until the drain current exceeds a current threshold. The circuit breaker is then charged further with a smaller charging current associated with the desired rate of rise, until the drain voltage falls below a predefined voltage threshold. The circuit breaker is then charged further with the high charging current for a predefined period. In order to close the circuit breaker, a nearly reverse sequence is followed.

    Abstract translation: 为了以兼容的电磁干扰来驱动它，断路器充电高电流，直到漏极电流超过电流阈值。 然后断路器进一步用与期望的上升速率相关联的更小的充电电流进行充电，直到漏极电压下降到预定电压阈值以下。 然后断路器进一步用高充电电流进一步充电预定的时间。 为了关闭断路器，遵循几乎相反的顺序。

    Direct memory access (DMA) data transfer requiring no processor DMA support
    80.
    发明授权
    Direct memory access (DMA) data transfer requiring no processor DMA support 失效
    直接存储器访问（DMA）数据传输，不需要处理器DMA支持

    公开(公告)号：US06134642A

    公开(公告)日：2000-10-17

    申请号：US698191

    申请日：1996-08-15

    Applicant: Anthony John Holmes ,  Mark Elliott ,  Ian Nicholas Cottam ,  John Harper ,  Martin Stratford

    Inventor： Anthony John Holmes ,  Mark Elliott ,  Ian Nicholas Cottam ,  John Harper ,  Martin Stratford

    IPC: G06F13/28 ,  G06F13/14

    CPC classification number: G06F13/28

    Abstract: A digital system has a main memory 10 with a main memory access (DMA) unit 11 through which data channels 12, 13 are coupled to the memory. A processor system (processor 14, RAM data memory 15, instruction memory 16) is also coupled to the memory through a read/write buffer 20, each read stalling the processor for typically 5 cycles. For block reads, a block memory read unit 25 is connected in parallel with the path between the read/write buffer 20 and the DMA unit 11. This block read unit can be set from the processor 14 with a block start address and a block length passed as writes through the read/write buffer 20. The block is read (first phase) word by word from the main memory via the DMA unit into a memory 28 in the block read unit. The processor then sends a command to the block read unit as a read through the read/write buffer, which then writes the block word by word directly into the memory 15 (second phase), using the processor's local data and address buses 17 and 18 and disabling the processor's address buffer 32.

    Abstract translation: 数字系统具有主存储器10，其具有主存储器访问（DMA）单元11，数据通道12,13通过该存储器访问（DMA）单元11耦合到存储器。 处理器系统（处理器14，RAM数据存储器15，指令存储器16）也通过读/写缓冲器20耦合到存储器，每个读取缓冲器读取停止处理器典型的5个周期。 对于块读取，块存储器读取单元25与读/写缓冲器20和DMA单元11之间的路径并联连接。该块读取单元可以从处理器14以块起始地址和块长度 通过读/写缓冲器20作为写入传递。该块从主存储器经由DMA单元逐字地读取（第一阶段）到块读取单元中的存储器28。 然后处理器通过读/写缓冲器向块读单元发送命令作为读/写缓冲器，该缓冲器然后使用处理器的本地数据和地址总线17和18将块逐字写入存储器15（第二阶段） 并禁用处理器的地址缓冲器32。

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