公开(公告)号：US20230070538A1

公开(公告)日：2023-03-09

申请号：US17942821

申请日：2022-09-12

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer

IPC: G06F3/06 ,  G06F12/10

Abstract: Methods, systems, and devices for valid data aware media reliability scanning are described. An apparatus may include a memory array comprising a plurality of blocks and a controller coupled with the memory array. The controller may be configured to select a block of the plurality of blocks for a scan operation to determine a margin of reliability for a first set of data stored in the block. The controller may identify information associated with a status of a validity of sub-blocks of the first set of data in the block. The controller may determine a first subset of the sub-blocks storing valid data of the first set of data and a second subset of sub-blocks that are invalid based on identifying the information. The controller may perform the scan operation on the first subset of sub-blocks and not on the second subset of sub-blocks in the block.

公开(公告)号：US20230041188A1

公开(公告)日：2023-02-09

申请号：US17397799

申请日：2021-08-09

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  David Aaron Palmer

IPC: G06F12/0893

Abstract: Methods, systems, and devices for cache block budgeting techniques are described. In some memory systems, a controller may configure a memory device with a cache. The cache may include a first subset of blocks configured to statically operate in a first mode and a second subset of blocks configured to dynamically switch between operating in the first mode and a second mode. A block operating in the second mode may be configured to store relatively more bits per memory cell than a block operating in the first mode. The controller may track and store, for each block of the second subset of blocks, a respective ratio of cycles performed in the first mode to cycles performed in the second mode. The controller may select a block from the second subset of blocks to switch between modes responsive to a trigger and based on the respective ratio for the block.

公开(公告)号：US20220229578A1

公开(公告)日：2022-07-21

申请号：US17153068

申请日：2021-01-20

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer

IPC: G06F3/06 ,  G06F12/10

Abstract: Methods, systems, and devices for valid data aware media reliability scanning are described. An apparatus may include a memory array comprising a plurality of blocks and a controller coupled with the memory array. The controller may be configured to select a block of the plurality of blocks for a scan operation to determine a margin of reliability for a first set of data stored in the block. The controller may identify information associated with a status of a validity of sub-blocks of the first set of data in the block. The controller may determine a first subset of the sub-blocks storing valid data of the first set of data and a second subset of sub-blocks that are invalid based on identifying the information. The controller may perform the scan operation on the first subset of sub-blocks and not on the second subset of sub-blocks in the block.

公开(公告)号：US20220223189A1

公开(公告)日：2022-07-14

申请号：US17708629

申请日：2022-03-30

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer

IPC: G11C11/409 ,  G06F12/02 ,  G06F12/14 ,  G06F3/06

Abstract: Devices and techniques are disclosed herein for more efficiently exchanging large amounts of data between a host and a flash storage system. In an example, read commands or write commands can optionally include a file-type indicator. The file-type indicator can allow for exchange of data between the host and the flash storage system using a single record of a Flash Translation Layer (FTL) table or logical-to-physical (L2P) table, and where the amount of data can be much larger than the atomic unit associated with the flash storage system.

公开(公告)号：US20220197744A1

公开(公告)日：2022-06-23

申请号：US17690742

申请日：2022-03-09

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer

IPC: G06F11/10 ,  G06F3/06

Abstract: Aspects of the present disclosure configure a system component, such as memory sub-system controller, to defer performance of an error-correction parity calculation for a block of a memory components of the memory subsystem. In particular, a memory sub-system controller of some embodiments can defer (e.g., delay) performance of an error-correction parity calculation and can defer the error-correction parity calculation such that it is performed at a time when the memory sub-system satisfies an idle state condition.

公开(公告)号：US20220188244A1

公开(公告)日：2022-06-16

申请号：US17117907

申请日：2020-12-10

Applicant: Micron Technology, Inc.

Inventor： Sharath Chandra Ambula ,  David Aaron Palmer ,  Venkata Kiran Kumar Matturi ,  Sri Ramya Pinisetty ,  Sushil Kumar

IPC: G06F12/1009

Abstract: Methods, systems, and devices for dynamic logical page sizes for memory devices are described. A memory device may use an initial set of logical pages each having a same size and one or more logical-to-physical (L2P) tables to map logical addresses of the logical pages to the physical addresses of corresponding physical pages. As commands are received from a host device, the memory device may dynamically split a logical page to introduce smaller logic pages if the host device accesses data in chunk sizes smaller than the size of the logical page that is split. The memory device may maintain one or more additional L2P tables for each smaller logical page size that is introduced, along with one or more pointer tables to map between L2P tables and entries for larger logical page sizes and L2P tables and entries associated with smaller logical page sizes.

公开(公告)号：US20220179781A1

公开(公告)日：2022-06-09

申请号：US17113999

申请日：2020-12-07

Applicant: Micron Technology, Inc.

Inventor： Sharath Chandra Ambula ,  Sushil Kumar ,  David Aaron Palmer ,  Venkata Kiran Kumar Matturi ,  Sri Ramya Pinisetty

IPC: G06F12/02 ,  G06F12/0831

Abstract: Methods, systems, and devices for session-based memory operation are described. A memory system may determine that a logical address targeted by a read command is associated with a session table. The memory system may write the session table to a cache based on the logical address being associated with the session table. After writing the session table to the cache, the memory system may use the session table to determine one or more logical-to-physical (L2P) tables and write the one or more L2P tables to the cache. The memory system may use the L2L tables to perform address translation for logical addresses.

公开(公告)号：US11226907B2

公开(公告)日：2022-01-18

申请号：US16226078

申请日：2018-12-19

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer

IPC: G06F21/00 ,  G06F12/14 ,  G06F12/06 ,  G06F21/60

Abstract: Devices and techniques are disclosed herein for verifying host generated physical addresses at a memory device during a host-resident FTL mode of operation to ameliorate erroneous or potentially malicious access to the memory device.

公开(公告)号：US11226894B2

公开(公告)日：2022-01-18

申请号：US16230313

申请日：2018-12-21

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer ,  Christian M. Gyllenskog ,  Jonathan Scott Parry ,  Stephen Hanna

IPC: G06F12/00 ,  G06F12/02 ,  G06F3/06 ,  G06F13/00 ,  G06F13/28

Abstract: Devices and techniques are disclosed herein for allowing host-based maintenance of a flash memory device. In certain examples, memory write information can be encrypted at the memory device and provided to the host for updating and maintaining memory device maintenance statistics.

公开(公告)号：US20210342263A1

公开(公告)日：2021-11-04

申请号：US17378212

申请日：2021-07-16

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  Qing Liang ,  David Aaron Palmer

IPC: G06F12/02

Abstract: Systems and methods for adapting garbage collection (GC) operations in a memory device to a host write activity are described. A host write progress can be represented by an actual host write count relative to a target host write count. The host write activity may be estimated in a unit time such as per day, or accumulated over a specified time period. A memory controller can adjust an amount of memory space to be freed by a GC operation according to the host write progress. The memory controller can also dynamically reallocate a portion of the memory cells between a single level cell (SLC) cache and a multi-level cell (MLC) storage according to the host write progress.