公开(公告)号：US11575896B2

公开(公告)日：2023-02-07

申请号：US17120995

申请日：2020-12-14

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Hideo Saitou ,  Masato Ohkawa ,  Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Yusuke Kato

IPC: H04N19/18 ,  H04N19/124 ,  H04N19/136 ,  H04N19/176 ,  H04N19/182

Abstract: An encoder includes circuitry and memory coupled to the circuitry. The circuitry, in operation: generates (i) a first quantization matrix for transform coefficients included in a current block to be processed and (ii) a second quantization matrix for transform coefficients included in a low frequency domain among the transform coefficients included in the current block; and quantizes the transform coefficients included in the current block using at least one of the first quantization matrix or the second quantization matrix, in accordance with a size of the current block.

公开(公告)号：US11546591B2

公开(公告)日：2023-01-03

申请号：US17667871

申请日：2022-02-09

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Jing Ya Li ,  Chong Soon Lim ,  Hai Wei Sun ,  Han Boon Teo ,  Che Wei Kuo ,  Chu Tong Wang ,  Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Yusuke Kato

IPC: H04N19/82 ,  H04N19/117 ,  H04N19/105 ,  H04N19/119 ,  H04N19/124 ,  H04N19/13 ,  H04N19/18 ,  H04N19/186

Abstract: An encoder includes circuitry and memory. The circuitry, in operation, generates a first coefficient value by applying a CCALF (cross component adaptive loop filtering) process to a first reconstructed image sample of a luma component. The circuitry generates a second coefficient value by applying an ALF (adaptive loop filtering) process to a second reconstructed image sample of a chroma component. The circuitry generates a third coefficient value by adding the first coefficient value to the second coefficient value, and encodes a third reconstructed image sample of the chroma component using the third coefficient value. In the CCALF process, in response to a coordinate of the second reconstructed image sample being (x, y), coordinates of the first reconstructed image samples are (2x, 2y−1), (2x−1, 2y), (2x, 2y), (2x+1, 2y), (2x−1, 2y+1), (2x, 2y+1), (2x+1, 2y+1), and (2x, 2y+2).

公开(公告)号：US11533511B2

公开(公告)日：2022-12-20

申请号：US17591259

申请日：2022-02-02

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Masato Ohkawa ,  Hideo Saitou ,  Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Yusuke Kato

IPC: H04N19/112 ,  H04N19/12 ,  H04N19/16 ,  H04N19/186 ,  H04N19/60 ,  H04N19/119 ,  H04N19/17 ,  H04N19/184 ,  H04N19/30

Abstract: Provided is an encoder including: circuitry; and memory coupled to the circuitry. In operation, the circuitry: performs a mapping process of Luma Mapping with Chroma Scaling (LMCS) for transforming a first pixel value space applied to a luma display image signal into a second pixel value space applied to a luma encoding process signal, using line segments forming a transform curve, each of which corresponds to a different one of sections obtained by partitioning the first pixel value space; and encodes an image, and in the performing of the LMCS, the circuitry determines the transform curve so that among boundary values in the second pixel value space, a first value obtained by dividing a boundary value by a base width defined according to a bit depth of the image is not equal to a second value obtained by dividing another boundary value by the base width.

公开(公告)号：US20220201306A1

公开(公告)日：2022-06-23

申请号：US17691623

申请日：2022-03-10

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Yusuke Kato ,  Kiyofumi Abe ,  Tadamasa Toma ,  Takahiro Nishi

IPC: H04N19/13 ,  H04N19/105 ,  H04N19/91 ,  H04N19/176 ,  H04N19/46

Abstract: An encoder includes circuitry and memory coupled to the circuitry. In residual coding of a current block to which an orthogonal transform is not applied, when coefficient information flags relating to a coefficient in the current block are encoded, the circuitry: performs a level mapping process to transform the coefficient to a second coefficient by using a predicted value, in which the predicted value is determined based on neighboring coefficients of the coefficient within the current block; encodes second coefficient information flags by Context-based Adaptive Binary Arithmetic Coding (CABAC), each of the second coefficient information flags relating to the second coefficient; and encodes a remainder value of the coefficient with Golomb-Rice code, and when the coefficient information flags are not encoded, in operation, the circuitry: skips the level mapping process; and encodes a value of the coefficient with the Golomb-Rice code.

公开(公告)号：US20220094974A1

公开(公告)日：2022-03-24

申请号：US17537930

申请日：2021-11-30

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Tadamasa Toma ,  Takahiro Nishi ,  Kiyofumi Abe ,  Yusuke Kato

IPC: H04N19/577 ,  H04N19/513 ,  H04N19/176

Abstract: Provided is an encoder including: circuitry; and memory coupled to the circuitry. The circuitry: derives a gradient value using a common deriving method shared between a case where a prediction image to be used to encode a current block is generated according to a bi-directional optical flow (BDOF) and a case where the prediction image is generated according to a prediction refinement with optical flow (PROF); and generates the prediction image using the gradient value in both the case where the prediction image is generated according to the BDOF and the case where the prediction image is generated according to the PROF, and in the common deriving method, the gradient value is derived by performing a subtraction process after performing a shift operation process.

公开(公告)号：US11102483B2

公开(公告)日：2021-08-24

申请号：US16875542

申请日：2020-05-15

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Chong Soon Lim ,  Hai Wei Sun ,  Han Boon Teo ,  Jing Ya Li ,  Che-Wei Kuo ,  Tadamasa Toma ,  Takahiro Nishi ,  Kiyofumi Abe ,  Yusuke Kato

IPC: H04N19/119 ,  H04N19/503 ,  H04N19/186 ,  H04N19/593 ,  H04N19/117 ,  H04N19/91 ,  H04N19/124 ,  H04N19/176

Abstract: An encoder includes circuitry and memory coupled to the circuitry. The circuitry determines whether to split a current luma virtual pipeline decoding unit (VPDU) into smaller blocks. When it is determined not to split the current luma VPDU into smaller blocks, scaling prediction residuals of chroma samples based on prediction residuals of luma samples is not performed. When it is determined to split the luma VPDU into smaller blocks, scaling the prediction residuals of chroma samples based on prediction residuals of luma samples is performed. The block is encoded based on the prediction residuals of chroma samples.

公开(公告)号：US12225220B2

公开(公告)日：2025-02-11

申请号：US17684657

申请日：2022-03-02

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Yusuke Kato

IPC: H04N19/423 ,  H04N19/159 ,  H04N19/176 ,  H04N19/82

Abstract: An encoder includes circuitry and memory coupled to the circuitry. In operation, the circuitry determines one or more tiles included in a picture and one or more subpictures included in the picture, according to a constraint condition that each tile of the one or more tiles includes at least one subpicture of the one or more subpictures entirely and the each tile does not include another subpicture of the one or more subpictures partially.

公开(公告)号：US12177438B2

公开(公告)日：2024-12-24

申请号：US18311064

申请日：2023-05-02

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Tadamasa Toma ,  Takahiro Nishi ,  Kiyofumi Abe ,  Yusuke Kato

IPC: H04N19/124 ,  H04N19/136 ,  H04N19/157 ,  H04N19/176 ,  H04N19/61

Abstract: An encoder includes circuitry and memory coupled to the circuitry. In operation, the circuitry: performs quantization on a plurality of transform coefficients of a current block to be encoded, using a quantization matrix when orthogonal transform is performed on the current block and secondary transform is not performed on the current block; and performs quantization on the plurality of transform coefficients of the current block without using the quantization matrix when orthogonal transform is not performed on the current block and when both orthogonal transform and secondary transform are performed on the current block.

公开(公告)号：US12149745B2

公开(公告)日：2024-11-19

申请号：US17834194

申请日：2022-06-07

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Takahiro Nishi ,  Tadamasa Toma ,  Kiyofumi Abe ,  Yusuke Kato

IPC: H04N19/70 ,  H04N19/105 ,  H04N19/154 ,  H04N19/169 ,  H04N19/172 ,  H04N19/29 ,  H04N19/30

Abstract: An encoder includes circuitry and memory coupled to the circuitry. In operation, for a group of layers including at least one output layer, the circuitry generates a bitstream including a common header for one or more layers in the group of layers, in which when a total number of layers in the group of layers is 1, (i) performance requirement information indicating a performance requirement for a decoder is signaled in the common header, and (ii) a hypothetical reference decoder (HRD) parameter is not signaled in the common header. The bitstream includes the common header and encoded data of at least one image in the at least one output layer. The common header does not include the HRD parameter.

公开(公告)号：US20240333934A1

公开(公告)日：2024-10-03

申请号：US18738296

申请日：2024-06-10

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi ABE ,  Takahiro Nishi ,  Tadamasa Toma ,  Yusuke Kato

IPC: H04N19/13 ,  H04L65/70 ,  H04L65/75 ,  H04N19/176 ,  H04N19/184 ,  H04N19/70

CPC classification number: H04N19/13 ,  H04L65/70 ,  H04L65/75 ,  H04N19/176 ,  H04N19/184 ,  H04N19/70

Abstract: An encoder includes memory and circuitry which: (i) encodes an image block; (ii) when encoding the image block: binarizes coefficient information indicating coefficients of the image block; and controls whether to apply arithmetic encoding to a binary data string obtained by binarizing the coefficient information; and (iii) when binarizing the coefficient information: binarizes the coefficient information according to a first syntax structure when arithmetic encoding is applied to the data string and a predetermined condition is not satisfied; binarizes the coefficient information according to a second syntax structure when arithmetic encoding is applied to the data string and the predetermined condition is satisfied; binarizes the coefficient information according to the second syntax structure when no arithmetic encoding is applied to the data string; and subtracts 1 from a value of an initial non-zero coefficient when no arithmetic encoding is applied to the data string when encoding the image block.