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71.发明授权Chained cache coherency states for sequential non-homogeneous access to a cache line with outstanding data response 有权链接高速缓存一致性状态用于对具有出色数据响应的高速缓存行的顺序非均匀访问公开(公告)号：US07409504B2
公开(公告)日：2008-08-05
申请号：US11245312
申请日：2005-10-06
IPC分类号： G06F12/00
CPC分类号： G06F12/0831
摘要： A method for sequentially coupling successive processor requests for a cache line before the data is received in the cache of a first coupled processor. Both homogenous and non-homogenous operations are chained to each other, and the coherency protocol includes several new intermediate coherency responses associated with the chained states. Chained coherency states are assigned to track the chain of processor requests and the grant of access permission prior to receipt of the data at the first processor. The chained coherency states also identify the address of the receiving processor. When data is received at the cache of the first processor within the chain, the processor completes its operation on (or with) the data and then forwards the data to the next processor in the chain. The chained coherency protocol frees up address bus bandwidth by reducing the number of retries.
摘要翻译： 一种用于在数据在第一耦合处理器的高速缓存中接收数据之前顺序耦合高速缓存行的连续处理器请求的方法。 同质和非均匀的操作彼此链接，并且一致性协议包括与链接状态相关联的几个新的中间一致性响应。 分配链接一致性状态以在第一处理器接收到数据之前跟踪处理器请求链和授予访问权限。 链接的一致性状态还标识接收处理器的地址。 当在链中的第一处理器的高速缓存处接收到数据时，处理器完成其对数据的（或与）数据的操作，然后将数据转发到链中的下一个处理器。 链接的一致性协议通过减少重试次数来释放地址总线带宽。
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72.发明授权Method and system for reducing storage requirements of simulation data via keyword restrictions 有权通过关键词限制减少模拟数据存储需求的方法和系统公开(公告)号：US07373290B2
公开(公告)日：2008-05-13
申请号：US10388976
申请日：2003-03-13
IPC分类号： G06F9/44
CPC分类号： G06F17/5022
摘要： Disclosed herein is a method of managing data results of simulation processing of a hardware description language (HDL) model based upon keywords. In accordance with the method, a restriction list associated with the HDL model is received. The HDL model has a maximum number of possible keyword/value pairs sets for which result data can be obtained, and the restriction list specifies a fewer number of keyword/value pair sets for which the result data can be queried based upon at least one keyword. In response to receipt of result data obtained by simulation of the HDL model, the result data are stored within a data storage subsystem by reference to the restriction list, such that particular result data attributable to each of the plurality of keyword/value sets is separately accessible.
摘要翻译： 本文公开了一种基于关键字来管理硬件描述语言（HDL）模型的模拟处理的数据结果的方法。 根据该方法，接收与HDL模型相关联的限制列表。 HDL模型具有可以获得结果数据的可能的关键字/值对集合的最大数量，并且限制列表指定少量关键字/值对集合，根据至少一个关键字可以查询结果数据 。 响应于接收到通过HDL模型的模拟而获得的结果数据，结果数据通过参考限制表被存储在数据存储子系统内，使得归因于多个关键字/值集合中的每一个的特定结果数据是分开的 无障碍。
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73.发明授权Method for priority scheduling and priority dispatching of store conditional operations in a store queue 有权存储条件操作在存储队列中的优先级调度和优先级调度的方法公开(公告)号：US07360041B2
公开(公告)日：2008-04-15
申请号：US10970437
申请日：2004-10-21
IPC分类号： G06F12/00
CPC分类号： G06F9/30087 , G06F9/3004 , G06F9/3824 , G06F9/3834 , G06F9/3851
摘要： A method, system, and processor chip design for reducing the latency between completing a LARX operation and receiving the associated STCX operation to complete the update to the cache line. Each entry of the store queue of the issuing processor is provided an additional tracking bit (priority bit). The priority bit is set whenever a STCX operation is placed within the entry. During selection of an entry for dispatch by the arbitration logic, the arbitration logic scans the value of the priority bits of each eligible entry. An entry with the priority bit set is given priority in the selection process within architectural rules. That entry is then selected for dispatch as early as is possible within the established rules.
摘要翻译： 一种方法，系统和处理器芯片设计，用于减少完成LARX操作和接收相关联的STCX操作之间的延迟，以完成对高速缓存行的更新。 向发行处理器的存储队列的每个条目提供附加跟踪位（优先级位）。 每当在条目中放置STCX操作时，优先级位置位。 在选择由仲裁逻辑发送的条目期间，仲裁逻辑扫描每个合格条目的优先级位的值。 具有优先级位的条目在架构规则中的选择过程中被赋予优先级。 然后在既定规则内尽可能早地选择该条目进行发送。
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公开(公告)号：US07359847B2
公开(公告)日：2008-04-15
申请号：US09997460
申请日：2001-11-30
CPC分类号： G06F17/5022
摘要： A method and system for providing centralized access to count event information from testing of a hardware simulation model within a batch simulation farm which includes simulation clients and an instrumentation server. Count event data for said hardware simulation model is received by the instrumentation server from one or more simulation clients. A first and a second counter report are generated for the hardware simulation model, in which the first and second counter reports are derived from the count event data received by the instrumentation server. The first counter report is compared to the second counter report, and responsive to this comparison, a counter difference report is generated within the instrumentation server that conveys count event trends associated with the simulation model under different simulation testcases.
摘要翻译： 一种方法和系统，用于通过测试包含模拟客户端和仪器服务器的批量模拟场内的硬件仿真模型来提供集中访问计数事件信息。 所述硬件仿真模型的计数事件数据由仪器服务器从一个或多个仿真客户端接收。 为硬件仿真模型生成第一和第二计数器报告，其中第一和第二计数器报告是从由仪器服务器接收的计数事件数据导出的。 将第一个计数器报告与第二个计数器报告进行比较，并根据此比较，在仪表服务器内生成一个反差异报告，传达与不同模拟测试用例下的仿真模型相关的计数事件趋势。
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75.发明授权Processor, data processing system and method for synchronizing access to data in shared memory 有权处理器，数据处理系统和方法，用于同步共享存储器中数据的访问公开(公告)号：US07228385B2
公开(公告)日：2007-06-05
申请号：US10965113
申请日：2004-10-14
IPC分类号： G06F12/00
CPC分类号： G06F9/3834 , G06F9/3004 , G06F9/30072 , G06F9/30087 , G06F9/3851 , G06F12/0811 , G06F12/0831 , G06F12/0855
摘要： A processing unit for a multiprocessor data processing system includes a store-through upper level cache, an instruction sequencing unit that fetches instructions for execution, at least one instruction execution unit that executes a store-conditional instruction to determine a store target address, a store queue that, following execution of the store-conditional instruction, buffers a corresponding store operation, sequencer logic associated with the store queue. The sequencer logic, responsive to receipt of a latency indication indicating that resolution of the store-conditional operation as passing or failing is subject to significant latency, invalidates, prior to resolution of the store-conditional operation, a cache line in the store-through upper level cache to which a load-reserve operation previously bound.
摘要翻译： 一种用于多处理器数据处理系统的处理单元，包括存储器上级缓存器，取指令执行指令排序单元，至少一个执行存储条件指令以确定存储目标地址的指令执行单元，存储器 在存储条件指令的执行之后，缓存与存储队列相关联的对应存储操作，定序器逻辑的队列。 定序器逻辑响应于指示存储条件操作的解析作为传递或失败的等待时间指示受到重大等待时间的影响，在存储条件操作的解析之前无效，存储器中的高速缓存行 加载预备操作先前绑定到的高级缓存。
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76.发明授权Method, system and program product for specifying and using register entities to configure a simulated or physical digital system 失效用于指定和使用寄存器实体配置模拟或物理数字系统的方法，系统和程序产品公开(公告)号：US07213225B2
公开(公告)日：2007-05-01
申请号：US10857461
申请日：2004-05-28
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/505
摘要： In at least one hardware definition language (HDL) file, at least one design entity containing a functional portion of a digital system is specified. The design entity logically contains first and second latches each having a respective plurality of different possible latch values. With one or more statements, a first Dial instance is associated with the first latch and a second Dial instance is associated with the second latch. A setting of the first Dial instance thus controls which of the plurality of different possible values is loaded in the first latch, and a setting of the second Dial instance controls which of the plurality of different possible values is loaded in the second latch. With a statement, a Register instance is concurrently associated with both the first and the second latches, such that a setting of the Register instance controls the latch values loaded in both the first and second latches.
摘要翻译： 在至少一个硬件定义语言（HDL）文件中，指定包含数字系统的功能部分的至少一个设计实体。 设计实体逻辑地包含第一和第二锁存器，每个锁存器具有相应的多个不同的可能锁存值。 利用一个或多个语句，第一拨号实例与第一锁存器相关联，并且第二拨号实例与第二锁存器相关联。 因此，第一拨号实例的设置控制多个不同可能值中的哪一个加载到第一锁存器中，并且第二拨号实例的设置控制多个不同可能值中的哪一个加载到第二锁存器中。 通过语句，寄存器实例同时与第一和第二锁存器相关联，使得寄存器实例的设置控制加载在第一和第二锁存器中的锁存值。
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77.发明授权Method and system for selectively storing and retrieving simulation data utilizing keywords 失效使用关键词选择性地存储和检索模拟数据的方法和系统公开(公告)号：US07203633B2
公开(公告)日：2007-04-10
申请号：US10366438
申请日：2003-02-13
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： Disclosed herein is a method of storing data results of simulation processing of a hardware description language (HDL) model based upon keywords. In accordance with the method, result data obtained by simulation of at least one HDL model are received. In association with the result data, a plurality of value sets is received, where each value set includes at least one keyword having an associated value. Each keyword identifies a parameter external to the HDL model that affected the result data. The data results are stored within a data storage subsystem in association with the plurality of value sets such that particular result data are attributable to particular ones of the plurality of value sets. In one embodiment, a keyword table is built in the data storage system that indicates which data subdirectories store result data associated with particular value sets. The result data can then be queried based upon selected keywords of interest, for example, by reference to the keyword table.
摘要翻译： 本文公开了一种基于关键字存储硬件描述语言（HDL）模型的模拟处理的数据结果的方法。 根据该方法，接收通过模拟至少一个HDL模型获得的结果数据。 与结果数据相关联，接收多个值集合，其中每个值集合包括至少一个具有关联值的关键字。 每个关键字标识影响结果数据的HDL模型外部的参数。 数据结果与多个值集合相关联地存储在数据存储子系统中，使得特定结果数据可归因于多个值集合中的特定值。 在一个实施例中，在数据存储系统中建立关键字表，其指示哪些数据子目录存储与特定值集相关联的结果数据。 然后，可以基于所选择的感兴趣的关键字来查询结果数据，例如通过参考关键字表来查询结果数据。
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78.发明授权Method, system and program product for configuring a simulation model of a digital design 失效用于配置数字设计仿真模型的方法，系统和程序产品公开(公告)号：US07162404B2
公开(公告)日：2007-01-09
申请号：US10425041
申请日：2003-04-28
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5022
摘要： A configuration database associated with a digital design stores at least one data structure defining a Dial instance and a mapping between each possible input value of the Dial instance and a respective output value. The output value controls which of a number of different possible latch values is placed in a configuration latch to configure a functional portion of a simulation model of the digital design. The configuration database further indicates an association between the Dial instance and the configuration latch. In response to a request specifying an input value for the Dial instance, the data structure in the configuration database is accessed to determine an output value for the Dial instance based upon the mapping. In addition, a latch value for the configuration latch is obtained based upon the output value and the association indicated by the configuration database. The latch value is then utilized to set the configuration latch in the simulation model.
摘要翻译： 与数字设计相关联的配置数据库存储定义Dial实例的至少一个数据结构以及Dial实例的每个可能的输入值与相应的输出值之间的映射。 输出值控制将多个不同可能的锁存值中的哪一个放置在配置锁存器中以配置数字设计的仿真模型的功能部分。 配置数据库还指示Dial实例和配置锁存器之间的关联。 响应于指定Dial实例的输入值的请求，访问配置数据库中的数据结构，以基于映射确定Dial实例的输出值。 此外，基于由配置数据库指示的输出值和关联来获得配置锁存器的锁存值。 然后使用锁存值在仿真模型中设置配置锁存器。
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79.发明授权公开(公告)号：US07143387B2
公开(公告)日：2006-11-28
申请号：US10651187
申请日：2003-08-28
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： Methods, data processing systems, and program products are disclosed that support the definition and accessing of links indicating a relationship between configuration construct instances, such as Dial and Dial group instances, within a digital design. According to one method, first and second latches within the digital design are specified in at least one HDL statement within one or more HDL files representing the digital design. In the one or more HDL files, a first configuration construct instance referencing the first latch and a second configuration construct instance referencing the second latch are also defined. The first and second configuration construct instances provide interfaces through which values of the first and second latches can be accessed. In addition, a link indicating a relationship between the first and second configuration construct instances is also defined within the one or more HDL files.
摘要翻译： 公开了支持在数字设计中指示配置构造实例（例如拨号和拨号组实例）之间的关系的链接的定义和访问的方法，数据处理系统和程序产品。 根据一种方法，数字设计中的第一和第二锁存器在表示数字设计的一个或多个HDL文件内的至少一个HDL语句中被指定。 在一个或多个HDL文件中，还定义了引用第一锁存器的第一配置结构实例和引用第二锁存器的第二配置结构实例。 第一和第二配置构造实例提供可以访问第一和第二锁存器的值的接口。 此外，还在一个或多个HDL文件内定义指示第一和第二配置构造实例之间的关系的链接。
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公开(公告)号：US07143019B2
公开(公告)日：2006-11-28
申请号：US09997802
申请日：2001-11-30
CPC分类号： G01R31/318357 , G01R31/318314 , G06F17/5022
摘要： A method and system for associating instrumentation data with a simulation model within a batch simulation farm in which a simulation client communicates with an instrumentation server to process simulation data with respect to the simulation model. In accordance with the method of the present invention, an instrumentation eventlist is delivered from the simulation client to the instrumentation server. The eventlist contains instrumentation event information for the simulation model. Next, within the instrumentation server, a digital signature is computed that uniquely identifies contents of the instrumentation eventlist as being associated with the simulation model. Responsive to receiving simulation data from the simulation client, the digital signature is utilized to associate the simulation data with the simulation model.
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